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https://github.com/hoglet67/AtomBusMon.git
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129 lines
4.0 KiB
VHDL
129 lines
4.0 KiB
VHDL
--************************************************************************************************
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-- Internal I/O registers (implemented inside the core) decoder/multiplexer
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-- for AVR core
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-- Version 1.3 (Special version for the JTAG OCD)
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-- Designed by Ruslan Lepetenok
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-- Modified 22.04.2004
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.AVRuCPackage.all;
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entity io_reg_file is port (
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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iowe : in std_logic;
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dbusout : in std_logic_vector(7 downto 0);
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sreg_fl_in : in std_logic_vector(7 downto 0);
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sreg_out : out std_logic_vector(7 downto 0);
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sreg_fl_wr_en : in std_logic_vector (7 downto 0); --FLAGS WRITE ENABLE SIGNALS
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spl_out : out std_logic_vector(7 downto 0);
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sph_out : out std_logic_vector(7 downto 0);
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sp_ndown_up : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
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sp_en : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
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rampz_out : out std_logic_vector(7 downto 0));
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end io_reg_file;
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architecture rtl of io_reg_file is
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signal sreg : std_logic_vector(7 downto 0);
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signal sph : std_logic_vector(7 downto 0);
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signal spl : std_logic_vector(7 downto 0);
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signal rampz : std_logic_vector(7 downto 0);
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signal sp_int : std_logic_vector(15 downto 0);
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signal sp_intp : std_logic_vector(15 downto 0);
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signal sp_intm : std_logic_vector(15 downto 0);
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signal sp_res : std_logic_vector(15 downto 0);
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begin
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sreg_write:process(cp2,ireset)
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begin
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if ireset='0' then
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sreg <= (others => '0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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for i in sreg'range loop
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if (sreg_fl_wr_en(i)='1' or (adr=SREG_Address and iowe='1')) then -- CLOCK ENABLE
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if iowe='1' then
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sreg(i) <= dbusout(i); -- FROM THE INTERNAL DATA BUS
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else
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sreg(i) <= sreg_fl_in(i); -- FROM ALU FLAGS
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end if;
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end if;
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end loop;
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end if;
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end if;
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end process;
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sreg_out <= sreg;
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sp_intp<=(sph&spl)+1;
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sp_intm<=(sph&spl)-1;
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sp_res<= sp_intm when sp_ndown_up='0' else sp_intp;
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spl_write:process(cp2,ireset)
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begin
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if ireset='0' then
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spl <= (others => '0');
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elsif (cp2='1' and cp2'event) then
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if (sp_en='1' or (adr=SPL_Address and iowe='1')) then -- CLOCK ENABLE
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if iowe='1' then
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spl <= dbusout; -- FROM THE INTERNAL DATA BUS
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else
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spl <= sp_res(7 downto 0); -- FROM SPL BUS
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end if;
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end if;
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end if;
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end process;
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spl_out <= spl;
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sph_write:process(cp2,ireset)
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begin
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if ireset='0' then
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sph <= (others => '0');
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elsif (cp2='1' and cp2'event) then
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if (sp_en='1' or (adr=SPH_Address and iowe='1')) then -- CLOCK ENABLE
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if iowe='1' then
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sph <= dbusout; -- FROM THE INTERNAL DATA BUS
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else
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sph <= sp_res(15 downto 8); -- FROM SPH BUS
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end if;
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end if;
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end if;
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end process;
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sph_out <= sph;
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rampz_write:process(cp2,ireset)
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begin
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if ireset='0' then
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rampz <= (others => '0');
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elsif (cp2='1' and cp2'event) then
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if (adr=RAMPZ_Address and iowe='1') then -- CLOCK ENABLE
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rampz <= dbusout; -- FROM THE INTERNAL DATA BUS
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end if;
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end if;
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end process;
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rampz_out <= rampz;
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end rtl;
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