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https://github.com/hoglet67/AtomBusMon.git
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348 lines
10 KiB
VHDL
348 lines
10 KiB
VHDL
--**********************************************************************************************
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-- General purpose register file for the AVR Core
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-- Version 1.4 (Special version for the JTAG OCD)
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-- Modified 22.04.2004
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.SynthCtrlPack.all; -- Synthesis control
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entity reg_file is port (
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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reg_rd_in : in std_logic_vector(7 downto 0);
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reg_rd_out : out std_logic_vector(7 downto 0);
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reg_rd_adr : in std_logic_vector(4 downto 0);
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reg_rr_out : out std_logic_vector(7 downto 0);
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reg_rr_adr : in std_logic_vector(4 downto 0);
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reg_rd_wr : in std_logic;
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post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
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pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
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reg_h_wr : in std_logic;
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reg_h_out : out std_logic_vector(15 downto 0);
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reg_h_adr : in std_logic_vector(2 downto 0); -- x,y,z
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reg_z_out : out std_logic_vector(15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
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);
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end reg_file;
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architecture RTL of reg_file is
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type register_file_type is array(0 to 25) of std_logic_vector(7 downto 0);
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type register_mux_type is array(0 to 31) of std_logic_vector(7 downto 0);
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signal register_file : register_file_type;
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signal r26h : std_logic_vector(7 downto 0);
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signal r27h : std_logic_vector(7 downto 0);
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signal r28h : std_logic_vector(7 downto 0);
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signal r29h : std_logic_vector(7 downto 0);
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signal r30h : std_logic_vector(7 downto 0);
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signal r31h : std_logic_vector(7 downto 0);
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signal register_wr_en : std_logic_vector(31 downto 0);
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signal sg_rd_decode : std_logic_vector (31 downto 0);
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signal sg_rr_decode : std_logic_vector (31 downto 0);
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signal sg_tmp_rd_data : register_mux_type;
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signal sg_tmp_rr_data : register_mux_type;
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signal sg_adr16_postinc : std_logic_vector (15 downto 0);
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signal sg_adr16_predec : std_logic_vector (15 downto 0);
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signal reg_h_in : std_logic_vector (15 downto 0);
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signal sg_tmp_h_data : std_logic_vector (15 downto 0);
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begin
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write_decode: for i in 0 to 31 generate
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register_wr_en(i) <= '1' when (i=reg_rd_adr and reg_rd_wr='1') else '0';
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end generate;
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rd_mux_decode: for i in 0 to 31 generate
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sg_rd_decode(i) <= '1' when (reg_rd_adr=i) else '0';
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end generate;
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rr_mux_decode: for i in 0 to 31 generate
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sg_rr_decode(i) <= '1' when (reg_rr_adr=i) else '0';
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end generate;
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reg_z_out <= r31h&r30h; -- R31:R30 OUTPUT FOR LPM/ELPM INSTRUCTIONS
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sg_tmp_rd_data(0) <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0');
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read_rd_mux: for i in 1 to 25 generate
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sg_tmp_rd_data(i) <= register_file(i) when sg_rd_decode(i)='1' else sg_tmp_rd_data(i-1);
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end generate;
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sg_tmp_rd_data(26) <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data(25);
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sg_tmp_rd_data(27) <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data(26);
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sg_tmp_rd_data(28) <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data(27);
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sg_tmp_rd_data(29) <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data(28);
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sg_tmp_rd_data(30) <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data(29);
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sg_tmp_rd_data(31) <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data(30);
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reg_rd_out <= sg_tmp_rd_data(31);
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sg_tmp_rr_data(0) <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0');
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read_rr_mux: for i in 1 to 25 generate
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sg_tmp_rr_data(i) <= register_file(i) when sg_rr_decode(i)='1' else sg_tmp_rr_data(i-1);
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end generate;
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sg_tmp_rr_data(26) <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data(25);
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sg_tmp_rr_data(27) <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data(26);
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sg_tmp_rr_data(28) <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data(27);
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sg_tmp_rr_data(29) <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data(28);
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sg_tmp_rr_data(30) <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data(29);
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sg_tmp_rr_data(31) <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data(30);
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reg_rr_out <= sg_tmp_rr_data(31);
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h_dat_mux_l:for i in 0 to 7 generate
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sg_tmp_h_data(i) <= (r26h(i) and reg_h_adr(0)) or (r28h(i) and reg_h_adr(1)) or (r30h(i) and reg_h_adr(2));
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end generate;
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h_dat_mux_h:for i in 8 to 15 generate
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sg_tmp_h_data(i) <= (r27h(i-8) and reg_h_adr(0)) or (r29h(i-8) and reg_h_adr(1)) or (r31h(i-8) and reg_h_adr(2));
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end generate;
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sg_adr16_postinc <= sg_tmp_h_data +1;
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sg_adr16_predec <= sg_tmp_h_data -1;
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-- OUTPUT TO THE ADDRESS BUS
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reg_h_out <= sg_adr16_predec when (pre_dec='1') else -- PREDECREMENT
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sg_tmp_h_data; -- NO PREDECREMENT
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-- TO REGISTERS
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reg_h_in <= sg_adr16_postinc when (post_inc='1') else -- POST INC
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sg_adr16_predec; -- PRE DEC
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-- Register file with global reset (for simulation)
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RegFileWithRst:if CResetRegFile generate
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R0_R25:process(cp2,ireset)
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begin
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if ireset='0' then
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for i in 0 to 25 loop
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register_file(i) <= (others =>'0');
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end loop;
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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for i in 0 to 25 loop
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if register_wr_en(i)='1' then
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register_file(i) <= reg_rd_in;
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end if;
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end loop;
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end if;
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end if;
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end process;
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-- R26 (LOW)
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R26:process(cp2,ireset)
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begin
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if ireset='0' then
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r26h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(26)='1' then
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r26h <= reg_rd_in;
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elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
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r26h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R27 (HIGH)
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R27:process(cp2,ireset)
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begin
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if ireset='0' then
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r27h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(27)='1' then
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r27h <= reg_rd_in;
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elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
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r27h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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-- R28 (LOW)
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R28:process(cp2,ireset)
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begin
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if ireset='0' then
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r28h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(28)='1' then
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r28h <= reg_rd_in;
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elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
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r28h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R29 (HIGH)
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R29:process(cp2,ireset)
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begin
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if ireset='0' then
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r29h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(29)='1' then
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r29h <= reg_rd_in;
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elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
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r29h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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-- R30 (LOW)
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R30:process(cp2,ireset)
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begin
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if ireset='0' then
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r30h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(30)='1' then
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r30h <= reg_rd_in;
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elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
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r30h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R31 (HIGH)
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R31:process(cp2,ireset)
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begin
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if ireset='0' then
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r31h <= (others =>'0');
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elsif (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(31)='1' then
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r31h <= reg_rd_in;
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elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
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r31h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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end generate;
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-- Register file without global reset (for synthesis)
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RegFileWithoutRst:if not CResetRegFile generate
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R0_R25:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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for i in 0 to 25 loop
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if register_wr_en(i)='1' then
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register_file(i) <= reg_rd_in;
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end if;
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end loop;
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end if;
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end if;
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end process;
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-- R26 (LOW)
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R26:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(26)='1' then
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r26h <= reg_rd_in;
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elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
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r26h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R27 (HIGH)
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R27:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(27)='1' then
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r27h <= reg_rd_in;
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elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
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r27h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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-- R28 (LOW)
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R28:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(28)='1' then
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r28h <= reg_rd_in;
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elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
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r28h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R29 (HIGH)
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R29:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(29)='1' then
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r29h <= reg_rd_in;
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elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
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r29h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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-- R30 (LOW)
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R30:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(30)='1' then
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r30h <= reg_rd_in;
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elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
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r30h <= reg_h_in(7 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- R31 (HIGH)
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R31:process(cp2)
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begin
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if (cp2='1' and cp2'event) then
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if (cp2en='1') then -- Clock enable
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if register_wr_en(31)='1' then
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r31h <= reg_rd_in;
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elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
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r31h <= reg_h_in(15 downto 8);
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end if;
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end if;
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end if;
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end process;
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end generate;
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end RTL;
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