mirror of
https://github.com/hoglet67/AtomBusMon.git
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43df61cd06
Change-Id: Ic21b05ae8ecb828d32e55fe36be501800cfb3407
215 lines
8.1 KiB
VHDL
215 lines
8.1 KiB
VHDL
--**********************************************************************************************
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-- Top entity for "Flash" programmer (for AVR Core)
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-- Version 0.3A
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-- Modified 31.05.2006
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.JTAGCompPack.all;
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entity JTAGOCDPrgTop is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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-- JTAG related inputs/outputs
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TRSTn : in std_logic; -- Optional
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TMS : in std_logic;
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TCK : in std_logic;
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TDI : in std_logic;
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TDO : out std_logic;
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TDO_OE : out std_logic;
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-- From the core
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PC : in std_logic_vector(15 downto 0);
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-- To the PM("Flash")
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pm_adr : out std_logic_vector(15 downto 0);
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pm_h_we : out std_logic;
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pm_l_we : out std_logic;
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pm_dout : in std_logic_vector(15 downto 0);
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pm_din : out std_logic_vector(15 downto 0);
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-- To the "EEPROM"
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EEPrgSel : out std_logic;
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EEAdr : out std_logic_vector(11 downto 0);
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EEWrData : out std_logic_vector(7 downto 0);
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EERdData : in std_logic_vector(7 downto 0);
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EEWr : out std_logic;
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-- CPU reset
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jtag_rst : out std_logic
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);
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end JTAGOCDPrgTop;
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architecture RTL of JTAGOCDPrgTop is
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-- From TCK clock domain to cp2 clock domain with resynchronization
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signal ChipEraseStart_TCK : std_logic;
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signal ChipEraseStart_cp2 : std_logic;
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signal ProgEnable_TCK : std_logic;
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signal ProgEnable_cp2 : std_logic;
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signal FlWrMStart_TCK : std_logic;
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signal FlWrMStart_cp2 : std_logic;
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signal FlWrSStart_TCK : std_logic;
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signal FlWrSStart_cp2 : std_logic;
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signal FlRdMStart_TCK : std_logic;
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signal FlRdMStart_cp2 : std_logic;
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signal FlRdSStart_TCK : std_logic;
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signal FlRdSStart_cp2 : std_logic;
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signal EEWrStart_TCK : std_logic;
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signal EEWrStart_cp2 : std_logic;
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signal EERdStart_TCK : std_logic;
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signal EERdStart_cp2 : std_logic;
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signal TAPCtrlTLR_TCK : std_logic;
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signal TAPCtrlTLR_cp2 : std_logic;
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-- From TCK clock domain to cp2 clock domain without resynchronization
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signal FlEEPrgAdr_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Address
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signal FlEEPrgWrData_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Data for write
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-- From cp2 clock domain to TCK clock domain with resynchronization
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signal ChipEraseDone_cp2 : std_logic;
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signal ChipEraseDone_TCK : std_logic;
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-- From cp2 clock domain to TCK clock domain without resynchronization
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signal FlPrgRdData_cp2 : std_logic_vector(15 downto 0); -- Flash Read Data
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signal EEPrgRdData_cp2 : std_logic_vector(7 downto 0); -- EEPROM Read Data
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begin
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OCDProgTCK_Inst:component OCDProgTCK port map(
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-- JTAG related inputs/outputs
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TRSTn => TRSTn,
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TMS => TMS,
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TCK => TCK,
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TDI => TDI,
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TDO => TDO,
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TDO_OE => TDO_OE,
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-- From/To cp2 clock domain("Flash" programmer)
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FlEEPrgAdr => FlEEPrgAdr_TCK,
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FlPrgRdData => FlPrgRdData_cp2,
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EEPrgRdData => EEPrgRdData_cp2,
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FlEEPrgWrData => FlEEPrgWrData_TCK,
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ChipEraseStart => ChipEraseStart_TCK,
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ChipEraseDone => ChipEraseDone_TCK,
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ProgEnable => ProgEnable_TCK,
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FlWrMStart => FlWrMStart_TCK,
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FlWrSStart => FlWrSStart_TCK,
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FlRdMStart => FlRdMStart_TCK,
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FlRdSStart => FlRdSStart_TCK,
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EEWrStart => EEWrStart_TCK,
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EERdStart => EERdStart_TCK,
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TAPCtrlTLR => TAPCtrlTLR_TCK,
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-- CPU reset
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jtag_rst => jtag_rst
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);
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OCDProgcp2_Inst:component OCDProgcp2 port map(
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-- AVR Control
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ireset => ireset,
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cp2 => cp2,
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-- From/To TCK clock domain("Flash" programmer)
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FlEEPrgAdr => FlEEPrgAdr_TCK,
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FlPrgRdData => FlPrgRdData_cp2,
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EEPrgRdData => EEPrgRdData_cp2,
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FlEEPrgWrData => FlEEPrgWrData_TCK,
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ChipEraseStart => ChipEraseStart_cp2,
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ChipEraseDone => ChipEraseDone_cp2,
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ProgEnable => ProgEnable_cp2,
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FlWrMStart => FlWrMStart_cp2,
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FlWrSStart => FlWrSStart_cp2,
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FlRdMStart => FlRdMStart_cp2,
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FlRdSStart => FlRdSStart_cp2,
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EEWrStart => EEWrStart_cp2,
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EERdStart => EERdStart_cp2,
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TAPCtrlTLR => TAPCtrlTLR_cp2,
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-- From the core
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PC => PC,
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-- To the PM("Flash")
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pm_adr => pm_adr,
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pm_h_we => pm_h_we,
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pm_l_we => pm_l_we,
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pm_dout => pm_dout,
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pm_din => pm_din,
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-- To the "EEPROM"
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EEPrgSel => EEPrgSel,
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EEAdr => EEAdr,
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EEWrData => EEWrData,
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EERdData => EERdData,
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EEWr => EEWr
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);
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-- Resynchronizers (TCK to cp2)
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ChipEraseStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => ChipEraseStart_TCK,
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DOut => ChipEraseStart_cp2
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);
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ProgEnable_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => ProgEnable_TCK,
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DOut => ProgEnable_cp2
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);
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FlWrMStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => FlWrMStart_TCK,
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DOut => FlWrMStart_cp2
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);
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FlWrSStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => FlWrSStart_TCK,
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DOut => FlWrSStart_cp2
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);
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FlRdMStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => FlRdMStart_TCK,
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DOut => FlRdMStart_cp2
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);
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FlRdSStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => FlRdSStart_TCK,
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DOut => FlRdSStart_cp2
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);
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EEWrStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => EEWrStart_TCK,
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DOut => EEWrStart_cp2
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);
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EERdStart_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => EERdStart_TCK,
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DOut => EERdStart_cp2
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);
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TAPCtrlTLR_Resync_Inst:component Resync1b_cp2 port map(
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cp2 => cp2,
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DIn => TAPCtrlTLR_TCK,
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DOut => TAPCtrlTLR_cp2
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);
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-- Resynchronizers (cp2 to TCK)
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ChipEraseDone_Resync_Inst:component Resync1b_TCK port map(
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TCK => TCK,
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DIn => ChipEraseDone_cp2,
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DOut => ChipEraseDone_TCK
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);
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end RTL; |