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https://github.com/hoglet67/AtomBusMon.git
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42 lines
1.1 KiB
VHDL
42 lines
1.1 KiB
VHDL
-- *****************************************************************************************
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--
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-- Version 0.14
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-- Modified 02.08.2005
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-- Designed by Ruslan Lepetenok
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-- *****************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package MemAccessCtrlPack is
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constant CNumOfBusMasters : positive := 3;
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constant CNumOfSlaves : positive := 2;
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constant CUseRAMSel : boolean := FALSE;
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-- Masters
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type MastOutBus_Type is record
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ramadr : std_logic_vector(15 downto 0);
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dout : std_logic_vector(7 downto 0);
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ramre : std_logic;
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ramwe : std_logic;
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end record;
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type MastersOutBus_Type is array(CNumOfBusMasters-1 downto 0) of MastOutBus_Type;
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-- Slave
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type SlvOutBus_Type is record
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dout : std_logic_vector(7 downto 0);
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out_en : std_logic;
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end record;
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type SlavesOutBus_Type is array(CNumOfSlaves-1 downto 0) of SlvOutBus_Type;
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-- Memory address decoder
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constant CMemMappedIOBaseAdr : std_logic_vector(3 downto 0) := x"D";
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constant CDRAMBaseAdr : std_logic_vector(1 downto 0) := "00";
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end MemAccessCtrlPack; |