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30 lines
899 B
VHDL
30 lines
899 B
VHDL
--************************************************************************************************
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-- Component declaration for the synchronizer
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-- Version 0.2
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-- Designed by Ruslan Lepetenok
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-- Modified 10.08.2003
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package SynchronizerCompPack is
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-- Transparent D latch
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component SynchronizerLatch is port(
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D : in std_logic;
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G : in std_logic;
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Q : out std_logic;
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QN : out std_logic);
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end component;
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-- Falling edge triggered flip-flop
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component SynchronizerDFF is port(
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NRST : in std_logic;
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CLK : in std_logic;
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D : in std_logic;
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Q : out std_logic);
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end component;
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end SynchronizerCompPack;
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