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https://github.com/hoglet67/AtomBusMon.git
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124 lines
4.4 KiB
VHDL
124 lines
4.4 KiB
VHDL
--**********************************************************************************************
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-- Parallel Port Peripheral for the AVR Core
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-- Version 0.7
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-- Modified 10.08.2003
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-- Designed by Ruslan Lepetenok.
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--
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-- The possibility of implementing level sensitive LATCH instead of edge sensitive DFF
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-- (for the first stage of the synchronizer) is added.
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.AVRuCPackage.all;
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use WORK.SynthCtrlPack.all; -- Synthesis control
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use WORK.SynchronizerCompPack.all; -- Component declarations for the synchronizers
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entity pport is generic(PPortNum : natural);
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port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- --Info
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-- miso_LOC : in integer;
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-- spi_spe : in std_logic;
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-- External connection
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-- spi_misoi : out std_logic;
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portx : out std_logic_vector(7 downto 0);
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ddrx : out std_logic_vector(7 downto 0);
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pinx : in std_logic_vector(7 downto 0);
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irqlines : out std_logic_vector(7 downto 0));
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end pport;
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architecture RTL of pport is
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signal PORTx_Int : std_logic_vector(portx'range);
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signal DDRx_Int : std_logic_vector(ddrx'range);
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signal PINx_Tmp : std_logic_vector(pinx'range);
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signal PINx_Resync : std_logic_vector(pinx'range);
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signal PORTx_Sel : std_logic;
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signal DDRx_Sel : std_logic;
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signal PINx_Sel : std_logic;
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begin
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PORTx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Port_Adr else '0';
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DDRx_Sel <= '1' when adr=PPortAdrArray(PPortNum).DDR_Adr else '0';
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PINx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
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--spi_misoi_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
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out_en <= (PORTx_Sel or DDRx_Sel or PINx_Sel) and iore;
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PORTx_DFF:process(cp2,ireset)
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begin
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if (ireset='0') then -- Reset
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PORTx_Int <= (others => '0');
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elsif (cp2='1' and cp2'event) then -- Clock
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if PORTx_Sel='1' and iowe='1' then -- Clock enable
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PORTx_Int <= dbus_in;
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end if;
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end if;
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end process;
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DDRx_DFF:process(cp2,ireset)
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begin
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if (ireset='0') then -- Reset
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DDRx_Int <= (others => '0');
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elsif (cp2='1' and cp2'event) then -- Clock
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if DDRx_Sel='1' and iowe='1' then -- Clock enable
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DDRx_Int <= dbus_in;
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end if;
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end if;
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end process;
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-- The first stage of the resynchronizer : DFF or Latch
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SynchDFF:if not CSynchLatchUsed generate
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PINxDFFSynchronizer:for i in pinx'range generate
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PINxDFFSynchronizer_Inst:component SynchronizerDFF port map(
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NRST => ireset,
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CLK => cp2,
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D => pinx(i),
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Q => PINx_Tmp(i));
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end generate;
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end generate;
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SynchLatch:if CSynchLatchUsed generate
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PINxLatchSynchronizer:for i in pinx'range generate
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PINxLatchSynchronizer_Inst:component SynchronizerLatch port map(
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D => pinx(i),
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G => cp2,
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Q => PINx_Tmp(i),
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QN => open);
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end generate;
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end generate;
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-- End of the first stage of the resynchronizer
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PINXInputReg:process(cp2,ireset)
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begin
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if (ireset='0') then -- Reset
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PINx_Resync <= (others => '0');
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elsif (cp2='1' and cp2'event) then -- Clock
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PINx_Resync <= PINx_Tmp;
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end if;
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end process;
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DBusOutMux:for i in pinx'range generate
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dbus_out(i) <= (PORTx_Int(i) and PORTx_Sel)or(DDRx_Int(i) and DDRx_Sel)or(PINx_Resync(i) and PINx_Sel);
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irqlines(i) <= PINx_Resync(i);
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--spi_misoi <= pinx(i) when miso_Loc = i and spi_spe = '1';
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end generate;
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-- Outputs
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portx <= PORTx_Int;
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ddrx <= DDRx_Int;
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end RTL;
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