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https://github.com/hoglet67/AtomBusMon.git
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46 lines
1.5 KiB
VHDL
46 lines
1.5 KiB
VHDL
--**********************************************************************************************
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--
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-- Version 0.1
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-- Modified 31.12.2006
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package spi_mod_comp_pack is
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component spi_mod is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- SPI i/f
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misoi : in std_logic;
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mosii : in std_logic;
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scki : in std_logic; -- Resynch
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ss_b : in std_logic; -- Resynch
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misoo : out std_logic;
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mosio : out std_logic;
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scko : out std_logic;
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spe : out std_logic;
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spimaster : out std_logic;
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-- IRQ
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spiirq : out std_logic;
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spiack : in std_logic;
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-- Slave Programming Mode
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por : in std_logic;
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spiextload : in std_logic;
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spidwrite : out std_logic;
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spiload : out std_logic
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);
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end component;
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end spi_mod_comp_pack;
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