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31 lines
1.1 KiB
VHDL
31 lines
1.1 KiB
VHDL
--**********************************************************************************************
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--
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-- Version 0.2
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-- Modified 10.01.2007
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package spi_slv_sel_comp_pack is
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component spi_slv_sel is generic(num_of_slvs : integer := 7);
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port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- Output
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slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
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);
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end component;
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end spi_slv_sel_comp_pack;
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