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https://github.com/hoglet67/AtomBusMon.git
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91 lines
4.4 KiB
VHDL
91 lines
4.4 KiB
VHDL
--************************************************************************************************
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-- Component declarations for AVR core (Bus Masters)
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-- Version 0.3
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-- Designed by Ruslan Lepetenok
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-- Modified 04.08.2005
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package BusMastCompPack is
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component uart_dma_top is port(
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-- Clock and reset
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ireset : in std_logic;
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cp2 : in std_logic;
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-- Data memory i/f (Slave part)
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stb_IO : in std_logic; -- SE
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stb_module : in std_logic; -- SE
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sramadr : in std_logic_vector(3 downto 0); -- ??
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sramre : in std_logic;
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sramwe : in std_logic;
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sram_dbus_out : out std_logic_vector(7 downto 0);
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sram_dbus_in : in std_logic_vector(7 downto 0);
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sram_dbus_out_en : out std_logic;
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-- Data memory i/f (Master part)
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mramadr : out std_logic_vector(15 downto 0);
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mramre : out std_logic;
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mramwe : out std_logic;
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mram_dbus_out : in std_logic_vector(7 downto 0);
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mram_dbus_in : out std_logic_vector(7 downto 0);
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mack : in std_logic;
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-- UART related ports
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adr : in std_logic_vector(5 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- Interrupts
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txcirq : out std_logic;
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txc_irqack : in std_logic;
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udreirq : out std_logic;
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udreirq_ack : in std_logic;
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rxcirq : out std_logic;
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rxcirq_ack : in std_logic;
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-- Wake up IRQ
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wupirq : out std_logic;
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wup_irqack : in std_logic;
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-- External connections
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rxd : in std_logic;
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txd : out std_logic;
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rx_en : out std_logic;
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tx_en : out std_logic;
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-- IE status
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ie_stat : out std_logic_vector(4 downto 0)
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);
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end component;
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component aescmdi_top is port(
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-- Clock and reset
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cp2 : in std_logic;
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ireset : in std_logic;
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-- RAM interface (Slave part)
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--ssel : in std_logic;
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stb_IO : in std_logic;
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stb_module : in std_logic;
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sramadr : in std_logic_vector(3 downto 0); -- ??
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sramre : in std_logic;
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sramwe : in std_logic;
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sram_dbus_out : out std_logic_vector(7 downto 0);
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sram_dbus_in : in std_logic_vector(7 downto 0);
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sram_dbus_out_en : out std_logic;
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-- RAM interface (Master part)
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mramadr : out std_logic_vector(15 downto 0);
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mramre : out std_logic;
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mramwe : out std_logic;
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mram_dbus_out : in std_logic_vector(7 downto 0);
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mram_dbus_in : out std_logic_vector(7 downto 0);
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mack : in std_logic;
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-- Interrupt support
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aes_irq : out std_logic;
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aes_irqack : in std_logic
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);
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end component;
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end BusMastCompPack;
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