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34 lines
1.0 KiB
VHDL
34 lines
1.0 KiB
VHDL
--**********************************************************************************************
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-- RAM data register for the AVR Core
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-- Version 0.1
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-- Modified 02.11.2002
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity RAMDataReg is port(
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ireset : in std_logic;
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cp2 : in std_logic;
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cpuwait : in std_logic;
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RAMDataIn : in std_logic_vector(7 downto 0);
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RAMDataOut : out std_logic_vector(7 downto 0)
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);
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end RAMDataReg;
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architecture RTL of RAMDataReg is
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begin
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RAMDataReg:process(cp2,ireset)
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begin
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if ireset='0' then -- Reset
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RAMDataOut <= (others => '0');
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elsif cp2='1' and cp2'event then -- Clock
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if cpuwait='0' then -- Clock enable
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RAMDataOut <= RAMDataIn;
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end if;
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end if;
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end process;
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end RTL;
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