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44 lines
1.6 KiB
VHDL
44 lines
1.6 KiB
VHDL
--************************************************************************************************
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-- External multeplexer for AVR core
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-- Version 2.2
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-- Designed by Ruslan Lepetenok 05.11.2001
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-- Modified 29.08.2003
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.AVRuCPackage.all;
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entity external_mux is port(
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ramre : in std_logic;
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dbus_out : out std_logic_vector(7 downto 0);
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ram_data_out : in std_logic_vector(7 downto 0);
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io_port_bus : in ext_mux_din_type;
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io_port_en_bus : in ext_mux_en_type;
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irqack : in std_logic;
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irqackad : in std_logic_vector(4 downto 0);
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ind_irq_ack : out std_logic_vector(22 downto 0)
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);
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end external_mux;
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architecture RTL of external_mux is
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signal ext_mux_out : ext_mux_din_type;
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begin
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ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
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data_mux_for_read:for i in 1 to ext_mux_out'high generate
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ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
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end generate;
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dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
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interrupt_ack:for i in ind_irq_ack'range generate
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ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
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end generate;
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end RTL;
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