mirror of
https://github.com/hoglet67/AtomBusMon.git
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6bb256b7ab
Change-Id: I3b426484bfad6843d6346064e0eb22b9bf3a9c82
565 lines
20 KiB
VHDL
Executable File
565 lines
20 KiB
VHDL
Executable File
-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 301 more merging
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-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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-- 65xx compatible microprocessor core
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--
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-- Version : 0246
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t65/
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--
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-- Limitations :
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--
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-- 65C02 and 65C816 modes are incomplete
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-- Undocumented instructions are not supported
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-- Some interface signals behaves incorrect
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--
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-- File history :
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--
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-- 0246 : First release
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T65_Pack.all;
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-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
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-- the ready signal to limit the CPU.
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entity T65 is
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
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Res_n : in std_logic;
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Enable : in std_logic;
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Clk : in std_logic;
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Rdy : in std_logic;
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Abort_n : in std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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SO_n : in std_logic;
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R_W_n : out std_logic;
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Sync : out std_logic;
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EF : out std_logic;
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MF : out std_logic;
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XF : out std_logic;
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ML_n : out std_logic;
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VP_n : out std_logic;
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VDA : out std_logic;
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VPA : out std_logic;
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A : out std_logic_vector(23 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0)
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);
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end T65;
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architecture rtl of T65 is
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-- Registers
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signal ABC, X, Y, D : std_logic_vector(15 downto 0);
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signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
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signal BAH : std_logic_vector(7 downto 0);
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signal BAL : std_logic_vector(8 downto 0);
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signal PBR : std_logic_vector(7 downto 0);
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signal DBR : std_logic_vector(7 downto 0);
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signal PC : unsigned(15 downto 0);
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signal S : unsigned(15 downto 0);
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signal EF_i : std_logic;
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signal MF_i : std_logic;
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signal XF_i : std_logic;
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signal IR : std_logic_vector(7 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal Mode_r : std_logic_vector(1 downto 0);
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signal ALU_Op_r : std_logic_vector(3 downto 0);
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signal Write_Data_r : std_logic_vector(2 downto 0);
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signal Set_Addr_To_r : std_logic_vector(1 downto 0);
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signal PCAdder : unsigned(8 downto 0);
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signal RstCycle : std_logic;
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signal IRQCycle : std_logic;
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signal NMICycle : std_logic;
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signal B_o : std_logic;
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signal SO_n_o : std_logic;
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signal IRQ_n_o : std_logic;
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signal NMI_n_o : std_logic;
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signal NMIAct : std_logic;
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signal Break : std_logic;
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-- ALU signals
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signal BusA : std_logic_vector(7 downto 0);
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signal BusA_r : std_logic_vector(7 downto 0);
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signal BusB : std_logic_vector(7 downto 0);
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signal ALU_Q : std_logic_vector(7 downto 0);
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signal P_Out : std_logic_vector(7 downto 0);
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-- Micro code outputs
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signal LCycle : std_logic_vector(2 downto 0);
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signal ALU_Op : std_logic_vector(3 downto 0);
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signal Set_BusA_To : std_logic_vector(2 downto 0);
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signal Set_Addr_To : std_logic_vector(1 downto 0);
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signal Write_Data : std_logic_vector(2 downto 0);
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signal Jump : std_logic_vector(1 downto 0);
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signal BAAdd : std_logic_vector(1 downto 0);
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signal BreakAtNA : std_logic;
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signal ADAdd : std_logic;
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signal AddY : std_logic;
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signal PCAdd : std_logic;
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signal Inc_S : std_logic;
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signal Dec_S : std_logic;
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signal LDA : std_logic;
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signal LDP : std_logic;
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signal LDX : std_logic;
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signal LDY : std_logic;
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signal LDS : std_logic;
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signal LDDI : std_logic;
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signal LDALU : std_logic;
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signal LDAD : std_logic;
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signal LDBAL : std_logic;
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signal LDBAH : std_logic;
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signal SaveP : std_logic;
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signal Write : std_logic;
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signal really_rdy : std_logic;
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signal R_W_n_i : std_logic;
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begin
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-- ehenciak : gate Rdy with read/write to make an "OK, it's
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-- really OK to stop the processor now if Rdy is
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-- deasserted" signal
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really_rdy <= Rdy or not(R_W_n_i);
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-- ehenciak : Drive R_W_n_i off chip.
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R_W_n <= R_W_n_i;
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Sync <= '1' when MCycle = "000" else '0';
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EF <= EF_i;
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MF <= MF_i;
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XF <= XF_i;
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ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
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VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
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VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
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VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
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mcode : T65_MCode
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port map(
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Mode => Mode_r,
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IR => IR,
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MCycle => MCycle,
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P => P,
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LCycle => LCycle,
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ALU_Op => ALU_Op,
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Set_BusA_To => Set_BusA_To,
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Set_Addr_To => Set_Addr_To,
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Write_Data => Write_Data,
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Jump => Jump,
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BAAdd => BAAdd,
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BreakAtNA => BreakAtNA,
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ADAdd => ADAdd,
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AddY => AddY,
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PCAdd => PCAdd,
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Inc_S => Inc_S,
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Dec_S => Dec_S,
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LDA => LDA,
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LDP => LDP,
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LDX => LDX,
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LDY => LDY,
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LDS => LDS,
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LDDI => LDDI,
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LDALU => LDALU,
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LDAD => LDAD,
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LDBAL => LDBAL,
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LDBAH => LDBAH,
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SaveP => SaveP,
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Write => Write
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);
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alu : T65_ALU
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port map(
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Mode => Mode_r,
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Op => ALU_Op_r,
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BusA => BusA_r,
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BusB => BusB,
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P_In => P,
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P_Out => P_Out,
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Q => ALU_Q
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);
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process (Res_n, Clk)
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begin
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if Res_n = '0' then
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PC <= (others => '0'); -- Program Counter
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IR <= "00000000";
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S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
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D <= (others => '0');
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PBR <= (others => '0');
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DBR <= (others => '0');
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Mode_r <= (others => '0');
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ALU_Op_r <= "1100";
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Write_Data_r <= "000";
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Set_Addr_To_r <= "00";
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R_W_n_i <= '1';
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EF_i <= '1';
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MF_i <= '1';
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XF_i <= '1';
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elsif Clk'event and Clk = '1' then
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if (Enable = '1') then
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if (really_rdy = '1') then
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R_W_n_i <= not Write or RstCycle;
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D <= (others => '1'); -- Dummy
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PBR <= (others => '1'); -- Dummy
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DBR <= (others => '1'); -- Dummy
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EF_i <= '0'; -- Dummy
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MF_i <= '0'; -- Dummy
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XF_i <= '0'; -- Dummy
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if MCycle = "000" then
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Mode_r <= Mode;
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if IRQCycle = '0' and NMICycle = '0' then
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PC <= PC + 1;
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end if;
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if IRQCycle = '1' or NMICycle = '1' then
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IR <= "00000000";
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else
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IR <= DI;
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end if;
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end if;
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ALU_Op_r <= ALU_Op;
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Write_Data_r <= Write_Data;
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if Break = '1' then
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Set_Addr_To_r <= "00";
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else
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Set_Addr_To_r <= Set_Addr_To;
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end if;
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if Inc_S = '1' then
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S <= S + 1;
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end if;
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if Dec_S = '1' and RstCycle = '0' then
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S <= S - 1;
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end if;
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if LDS = '1' then
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S(7 downto 0) <= unsigned(ALU_Q);
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end if;
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if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
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PC <= PC + 1;
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end if;
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--
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-- jump control logic
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--
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case Jump is
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when "01" =>
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PC <= PC + 1;
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when "10" =>
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PC <= unsigned(DI & DL);
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when "11" =>
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if PCAdder(8) = '1' then
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if DL(7) = '0' then
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PC(15 downto 8) <= PC(15 downto 8) + 1;
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else
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PC(15 downto 8) <= PC(15 downto 8) - 1;
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end if;
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end if;
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PC(7 downto 0) <= PCAdder(7 downto 0);
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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PCAdder <= resize(PC(7 downto 0), 9) + resize(unsigned(DL(7) & DL), 9) when PCAdd = '1'
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else "0" & PC(7 downto 0);
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process (Clk)
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begin
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if Clk'event and Clk = '1' then
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if (Enable = '1') then
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if (really_rdy = '1') then
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if MCycle = "000" then
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if LDA = '1' then
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ABC(7 downto 0) <= ALU_Q;
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end if;
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if LDX = '1' then
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X(7 downto 0) <= ALU_Q;
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end if;
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if LDY = '1' then
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Y(7 downto 0) <= ALU_Q;
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end if;
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if (LDA or LDX or LDY) = '1' then
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P <= P_Out;
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end if;
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end if;
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if SaveP = '1' then
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P <= P_Out;
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end if;
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if LDP = '1' then
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P <= ALU_Q;
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end if;
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if IR(4 downto 0) = "11000" then
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case IR(7 downto 5) is
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when "000" =>
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P(Flag_C) <= '0';
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when "001" =>
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P(Flag_C) <= '1';
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when "010" =>
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P(Flag_I) <= '0';
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when "011" =>
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P(Flag_I) <= '1';
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when "101" =>
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P(Flag_V) <= '0';
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when "110" =>
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P(Flag_D) <= '0';
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when "111" =>
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P(Flag_D) <= '1';
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when others =>
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end case;
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end if;
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--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
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-- P(Flag_B) <= '1';
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--end if;
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--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
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-- P(Flag_I) <= '1';
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-- P(Flag_B) <= B_o;
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--end if;
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-- B=1 always on the 6502
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P(Flag_B) <= '1';
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if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
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if MCycle = "011" then
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-- B=0 in *copy* of P pushed onto the stack
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P(Flag_B) <= '0';
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elsif MCycle = "100" then
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P(Flag_I) <= '1';
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end if;
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end if;
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if SO_n_o = '1' and SO_n = '0' then
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P(Flag_V) <= '1';
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end if;
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if RstCycle = '1' and Mode_r /= "00" then
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P(Flag_1) <= '1';
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P(Flag_D) <= '0';
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P(Flag_I) <= '1';
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end if;
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P(Flag_1) <= '1';
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B_o <= P(Flag_B);
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SO_n_o <= SO_n;
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IRQ_n_o <= IRQ_n;
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NMI_n_o <= NMI_n;
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end if;
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end if;
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end if;
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end process;
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---------------------------------------------------------------------------
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--
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-- Buses
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--
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---------------------------------------------------------------------------
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process (Res_n, Clk)
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begin
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if Res_n = '0' then
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BusA_r <= (others => '0');
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BusB <= (others => '0');
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AD <= (others => '0');
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BAL <= (others => '0');
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BAH <= (others => '0');
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DL <= (others => '0');
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elsif Clk'event and Clk = '1' then
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if (Enable = '1') then
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if (Rdy = '1') then
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BusA_r <= BusA;
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BusB <= DI;
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case BAAdd is
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when "01" =>
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-- BA Inc
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AD <= std_logic_vector(unsigned(AD) + 1);
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BAL <= std_logic_vector(unsigned(BAL) + 1);
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when "10" =>
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-- BA Add
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BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)), 9) + resize(unsigned(BusA), 9));
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when "11" =>
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-- BA Adj
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if BAL(8) = '1' then
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BAH <= std_logic_vector(unsigned(BAH) + 1);
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end if;
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when others =>
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end case;
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-- ehenciak : modified to use Y register as well (bugfix)
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if ADAdd = '1' then
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if (AddY = '1') then
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AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
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else
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AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
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end if;
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end if;
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if IR = "00000000" then
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BAL <= (others => '1');
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BAH <= (others => '1');
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if RstCycle = '1' then
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BAL(2 downto 0) <= "100";
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elsif NMICycle = '1' then
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BAL(2 downto 0) <= "010";
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else
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BAL(2 downto 0) <= "110";
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end if;
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if Set_addr_To_r = "11" then
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BAL(0) <= '1';
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end if;
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end if;
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if LDDI = '1' then
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DL <= DI;
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end if;
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if LDALU = '1' then
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DL <= ALU_Q;
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end if;
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if LDAD = '1' then
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AD <= DI;
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end if;
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if LDBAL = '1' then
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BAL(7 downto 0) <= DI;
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end if;
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if LDBAH = '1' then
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BAH <= DI;
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end if;
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end if;
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end if;
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end if;
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end process;
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Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
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with Set_BusA_To select
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BusA <= DI when "000",
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ABC(7 downto 0) when "001",
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X(7 downto 0) when "010",
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Y(7 downto 0) when "011",
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std_logic_vector(S(7 downto 0)) when "100",
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P when "101",
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(others => '-') when others;
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|
|
|
with Set_Addr_To_r select
|
|
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
|
|
DBR & "00000000" & AD when "10",
|
|
"00000000" & BAH & BAL(7 downto 0) when "11",
|
|
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
|
|
|
|
with Write_Data_r select
|
|
DO <= DL when "000",
|
|
ABC(7 downto 0) when "001",
|
|
X(7 downto 0) when "010",
|
|
Y(7 downto 0) when "011",
|
|
std_logic_vector(S(7 downto 0)) when "100",
|
|
P when "101",
|
|
std_logic_vector(PC(7 downto 0)) when "110",
|
|
std_logic_vector(PC(15 downto 8)) when others;
|
|
|
|
-------------------------------------------------------------------------
|
|
--
|
|
-- Main state machine
|
|
--
|
|
-------------------------------------------------------------------------
|
|
|
|
process (Res_n, Clk)
|
|
begin
|
|
if Res_n = '0' then
|
|
MCycle <= "001";
|
|
RstCycle <= '1';
|
|
IRQCycle <= '0';
|
|
NMICycle <= '0';
|
|
NMIAct <= '0';
|
|
elsif Clk'event and Clk = '1' then
|
|
if (Enable = '1') then
|
|
if (really_rdy = '1') then
|
|
if MCycle = LCycle or Break = '1' then
|
|
MCycle <= "000";
|
|
RstCycle <= '0';
|
|
IRQCycle <= '0';
|
|
NMICycle <= '0';
|
|
if NMIAct = '1' then
|
|
NMICycle <= '1';
|
|
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
|
|
IRQCycle <= '1';
|
|
end if;
|
|
else
|
|
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
|
|
end if;
|
|
|
|
if NMICycle = '1' then
|
|
NMIAct <= '0';
|
|
end if;
|
|
if NMI_n_o = '1' and NMI_n = '0' then
|
|
NMIAct <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end;
|