mirror of
https://github.com/hoglet67/AtomBusMon.git
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248 lines
9.7 KiB
VHDL
248 lines
9.7 KiB
VHDL
-- ****
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-- T80(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
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-- Ver 300 started tidyup
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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-- Z80 compatible microprocessor core
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--
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-- Version : 0250
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- Limitations :
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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package T80_Pack is
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constant aNone : std_logic_vector(2 downto 0) := "111";
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constant aBC : std_logic_vector(2 downto 0) := "000";
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constant aDE : std_logic_vector(2 downto 0) := "001";
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constant aXY : std_logic_vector(2 downto 0) := "010";
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constant aIOA : std_logic_vector(2 downto 0) := "100";
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constant aSP : std_logic_vector(2 downto 0) := "101";
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constant aZI : std_logic_vector(2 downto 0) := "110";
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component T80
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CEN : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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IORQ : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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DInst : in std_logic_vector(7 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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MC : out std_logic_vector(2 downto 0);
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TS : out std_logic_vector(2 downto 0);
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IntCycle_n : out std_logic;
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IntE : out std_logic;
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Stop : out std_logic;
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R800_mode : in std_logic := '0';
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out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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DIRSet : in std_logic := '0';
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DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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);
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end component;
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component T80_Reg
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port(
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Clk : in std_logic;
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CEN : in std_logic;
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WEH : in std_logic;
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WEL : in std_logic;
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AddrA : in std_logic_vector(2 downto 0);
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AddrB : in std_logic_vector(2 downto 0);
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AddrC : in std_logic_vector(2 downto 0);
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DIH : in std_logic_vector(7 downto 0);
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DIL : in std_logic_vector(7 downto 0);
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DOAH : out std_logic_vector(7 downto 0);
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DOAL : out std_logic_vector(7 downto 0);
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DOBH : out std_logic_vector(7 downto 0);
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DOBL : out std_logic_vector(7 downto 0);
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DOCH : out std_logic_vector(7 downto 0);
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DOCL : out std_logic_vector(7 downto 0);
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DOR : out std_logic_vector(127 downto 0);
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DIRSet : in std_logic;
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DIR : in std_logic_vector(127 downto 0)
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);
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end component;
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component T80_MCode
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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IR : in std_logic_vector(7 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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MCycle : in std_logic_vector(2 downto 0);
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F : in std_logic_vector(7 downto 0);
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NMICycle : in std_logic;
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IntCycle : in std_logic;
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XY_State : in std_logic_vector(1 downto 0);
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MCycles : out std_logic_vector(2 downto 0);
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TStates : out std_logic_vector(2 downto 0);
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Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
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Inc_PC : out std_logic;
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Inc_WZ : out std_logic;
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IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
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Read_To_Reg : out std_logic;
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Read_To_Acc : out std_logic;
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Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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ALU_Op : out std_logic_vector(3 downto 0);
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-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
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Save_ALU : out std_logic;
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Rot_Akku : out std_logic;
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PreserveC : out std_logic;
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Arith16 : out std_logic;
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Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
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IORQ : out std_logic;
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Jump : out std_logic;
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JumpE : out std_logic;
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JumpXY : out std_logic;
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Call : out std_logic;
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RstP : out std_logic;
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LDZ : out std_logic;
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LDW : out std_logic;
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LDSPHL : out std_logic;
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LDHLSP : out std_logic;
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ADDSPdd : out std_logic;
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Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
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ExchangeDH : out std_logic;
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ExchangeRp : out std_logic;
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ExchangeAF : out std_logic;
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ExchangeRS : out std_logic;
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I_DJNZ : out std_logic;
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I_CPL : out std_logic;
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I_CCF : out std_logic;
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I_SCF : out std_logic;
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I_RETN : out std_logic;
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I_BT : out std_logic;
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I_BC : out std_logic;
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I_BTR : out std_logic;
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I_RLD : out std_logic;
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I_RRD : out std_logic;
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I_INRC : out std_logic;
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I_MULUB : out std_logic;
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I_MULU : out std_logic;
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SetWZ : out std_logic_vector(1 downto 0);
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SetDI : out std_logic;
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SetEI : out std_logic;
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IMode : out std_logic_vector(1 downto 0);
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Halt : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic;
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R800_mode : in std_logic;
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No_PC : out std_logic;
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XYbit_undoc : out std_logic
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);
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end component;
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component T80_ALU
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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Arith16 : in std_logic;
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Z16 : in std_logic;
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WZ : in std_logic_vector(15 downto 0);
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XY_State : in std_logic_vector(1 downto 0);
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ALU_Op : in std_logic_vector(3 downto 0);
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Rot_Akku : in std_logic;
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IR : in std_logic_vector(5 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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F_In : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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F_Out : out std_logic_vector(7 downto 0)
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);
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end component;
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end;
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