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60 lines
2.0 KiB
VHDL
60 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity DCM2 is
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port (CLKIN_IN : in std_logic;
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RESET : in std_logic;
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CLKFX_OUT : out std_logic;
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LOCKED : out std_logic);
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end DCM2;
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architecture BEHAVIORAL of DCM2 is
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signal CLKFX_BUF : std_logic;
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signal CLKIN_IBUFG : std_logic;
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signal GND_BIT : std_logic;
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begin
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GND_BIT <= '0';
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CLKFX_BUFG_INST : BUFG
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port map (I => CLKFX_BUF, O => CLKFX_OUT);
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DCM_INST : DCM
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generic map(CLK_FEEDBACK => "NONE",
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CLKDV_DIVIDE => 4.0,
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CLKFX_DIVIDE => 1,
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CLKFX_MULTIPLY => 16,
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CLKIN_DIVIDE_BY_2 => false,
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CLKIN_PERIOD => 1000.00,
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CLKOUT_PHASE_SHIFT => "NONE",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => true,
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FACTORY_JF => x"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => false)
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port map (CLKFB => GND_BIT,
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CLKIN => CLKIN_IN,
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DSSEN => GND_BIT,
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PSCLK => GND_BIT,
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PSEN => GND_BIT,
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PSINCDEC => GND_BIT,
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RST => RESET,
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CLKDV => open,
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CLKFX => CLKFX_BUF,
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CLKFX180 => open,
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CLK0 => open,
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CLK2X => open,
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CLK2X180 => open,
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CLK90 => open,
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CLK180 => open,
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CLK270 => open,
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LOCKED => LOCKED,
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PSDONE => open,
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STATUS => open);
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end BEHAVIORAL;
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