2020-09-28 22:43:53 +00:00
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//
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// 6502Esque.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 28/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef m6502Esque_h
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#define m6502Esque_h
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2020-10-06 02:23:33 +00:00
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#include "../../ClockReceiver/ClockReceiver.hpp"
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2020-09-28 22:43:53 +00:00
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/*
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This file defines how the CPU-controlled part of a bus looks for the 6502 and
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for other processors with a sufficiently-similar bus.
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I'm not yet a big fan of the name I've used here, and I'm still on the fence
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about what to do when eventually I get around to the 6800 and/or 6809, which have
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very similar bus characteristics.
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So: this is _very_ provisional stuff.
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*/
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namespace CPU {
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namespace MOS6502Esque {
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2020-09-29 01:35:46 +00:00
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/*
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The list of registers that can be accessed via @c set_value_of_register and @c set_value_of_register.
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*/
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enum Register {
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LastOperationAddress,
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ProgramCounter,
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StackPointer,
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Flags,
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A,
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X,
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2020-10-14 01:38:30 +00:00
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Y,
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2020-10-16 01:35:01 +00:00
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// These exist on a 65816 only.
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2020-10-14 01:38:30 +00:00
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EmulationFlag,
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DataBank,
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ProgramBank,
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Direct
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2020-09-29 01:35:46 +00:00
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};
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2020-10-06 02:23:33 +00:00
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/*
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Flags as defined on the 6502; can be used to decode the result of @c get_value_of_register(Flags) or to form a value for
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the corresponding set.
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*/
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enum Flag: uint8_t {
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Sign = 0x80,
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Overflow = 0x40,
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Always = 0x20,
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Break = 0x10,
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Decimal = 0x08,
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Interrupt = 0x04,
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Zero = 0x02,
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2020-10-11 01:23:59 +00:00
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Carry = 0x01,
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// These are available on a 65816 only.
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MemorySize = 0x20,
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IndexSize = 0x10,
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2020-10-06 02:23:33 +00:00
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};
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2020-09-28 22:43:53 +00:00
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/*!
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Bus handlers will be given the task of performing bus operations, allowing them to provide whatever interface they like
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2020-10-16 01:35:01 +00:00
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between a 6502-esque chip and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
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2020-09-28 22:43:53 +00:00
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*/
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enum BusOperation {
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2020-10-16 01:35:01 +00:00
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/// 6502: indicates that a read was signalled.
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/// 65816: indicates that a read was signalled with VDA.
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2020-10-11 19:25:13 +00:00
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Read,
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2020-10-16 01:35:01 +00:00
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/// 6502: indicates that a read was signalled with SYNC.
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/// 65816: indicates that a read was signalled with VDA and VPA.
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2020-10-11 19:25:13 +00:00
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ReadOpcode,
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2020-10-16 01:35:01 +00:00
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/// 6502: never signalled.
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/// 65816: indicates that a read was signalled with VPA.
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ReadProgram,
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/// 6502: never signalled.
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2022-06-24 14:37:39 +00:00
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/// 65816: indicates that a read was signalled with VPB and VDA.
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2020-10-16 01:35:01 +00:00
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ReadVector,
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2020-10-17 01:56:20 +00:00
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/// 6502: never signalled.
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/// 65816: indicates that a read was signalled, but neither VDA nor VPA were active.
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InternalOperationRead,
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2020-10-16 01:35:01 +00:00
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2020-10-17 01:56:20 +00:00
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/// All processors: indicates that the processor is paused due to the RDY input.
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2020-10-16 01:35:01 +00:00
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/// 65C02 and 65816: indicates a WAI is ongoing.
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2020-10-11 19:25:13 +00:00
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Ready,
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2020-10-16 01:35:01 +00:00
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/// 65C02 and 65816: indicates a STP condition.
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None,
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2020-11-04 01:17:09 +00:00
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/// 6502: indicates that a write was signalled.
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/// 65816: indicates that a write was signalled with VDA.
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Write,
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/// 6502: never signalled.
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/// 65816: indicates that a write was signalled, but neither VDA nor VPA were active.
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InternalOperationWrite,
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2020-09-28 22:43:53 +00:00
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};
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/*!
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2020-10-17 01:56:20 +00:00
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For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise.
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2020-09-28 22:43:53 +00:00
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*/
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2020-10-18 02:27:04 +00:00
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#define isReadOperation(v) (v <= CPU::MOS6502Esque::InternalOperationRead)
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2020-09-28 22:43:53 +00:00
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2020-10-16 01:35:01 +00:00
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/*!
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2020-10-17 01:56:20 +00:00
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For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
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2020-10-16 01:35:01 +00:00
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*/
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2020-11-04 01:17:09 +00:00
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#define isWriteOperation(v) (v >= CPU::MOS6502Esque::Write)
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2020-10-16 01:35:01 +00:00
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/*!
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2020-10-17 01:56:20 +00:00
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Evaluates to @c true if the operation actually expects a response; @c false otherwise.
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2020-10-16 01:35:01 +00:00
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*/
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2020-11-04 01:17:09 +00:00
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#define isAccessOperation(v) ((v <= CPU::MOS6502Esque::ReadVector) || (v == CPU::MOS6502Esque::Write))
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2020-10-16 01:35:01 +00:00
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2020-09-28 22:43:53 +00:00
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/*!
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A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,
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machines should subclass BusHandler and then declare a realisation of the 6502 template, suplying their bus
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handler.
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*/
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2020-10-18 19:08:21 +00:00
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template <typename addr_t> class BusHandler {
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2020-09-28 22:43:53 +00:00
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public:
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2020-10-18 19:08:21 +00:00
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using AddressType = addr_t;
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2020-09-28 22:43:53 +00:00
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/*!
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Announces that the 6502 has performed the cycle defined by operation, address and value. On the 6502,
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all bus cycles take one clock cycle so the amoutn of time advanced is implicit.
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@param operation The type of bus cycle: read, read opcode (i.e. read, with sync active),
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write or ready.
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@param address The value of the address bus during this bus cycle.
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@param value If this is a cycle that puts a value onto the data bus, *value is that value. If this is
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a cycle that reads the bus, the bus handler should write a value to *value. Writing to *value during
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a read cycle will produce undefined behaviour.
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@returns The number of cycles that passed in objective time while this 6502 bus cycle was ongoing.
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On an archetypal machine this will be Cycles(1) but some architectures may choose not to clock the 6502
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during some periods; one way to simulate that is to have the bus handler return a number other than
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Cycles(1) to describe lengthened bus cycles.
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*/
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2020-10-18 19:08:21 +00:00
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Cycles perform_bus_operation([[maybe_unused]] BusOperation operation, [[maybe_unused]] addr_t address, [[maybe_unused]] uint8_t *value) {
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2020-09-28 22:43:53 +00:00
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return Cycles(1);
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}
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/*!
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Announces completion of all the cycles supplied to a .run_for request on the 6502. Intended to allow
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bus handlers to perform any deferred output work.
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*/
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void flush() {}
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};
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}
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}
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#endif /* m6502Esque_h */
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