2017-06-04 21:55:19 +00:00
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//
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// ZX8081.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/06/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "ZX8081.hpp"
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2017-06-05 14:36:07 +00:00
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#include "../MemoryFuzzer.hpp"
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2017-06-11 20:42:49 +00:00
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#include "../../Storage/Tape/Parsers/ZX8081.hpp"
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2017-06-05 13:38:49 +00:00
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2017-06-04 21:55:19 +00:00
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using namespace ZX8081;
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2017-06-06 14:13:32 +00:00
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namespace {
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2017-06-11 20:42:49 +00:00
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// The clock rate is 3.25Mhz.
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2017-06-06 14:13:32 +00:00
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const unsigned int ZX8081ClockRate = 3250000;
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}
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2017-06-04 22:32:23 +00:00
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Machine::Machine() :
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2017-06-05 01:54:55 +00:00
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vsync_(false),
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hsync_(false),
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2017-06-05 14:47:42 +00:00
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ram_(1024),
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2017-06-06 14:13:32 +00:00
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key_states_{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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tape_player_(ZX8081ClockRate) {
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set_clock_rate(ZX8081ClockRate);
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2017-06-05 14:36:07 +00:00
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Memory::Fuzz(ram_);
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2017-06-06 14:13:32 +00:00
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tape_player_.set_motor_control(true);
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2017-06-04 21:55:19 +00:00
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}
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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2017-06-06 21:53:23 +00:00
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video_->run_for_cycles(cycle.length);
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2017-06-06 14:13:32 +00:00
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tape_player_.run_for_cycles(cycle.length);
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2017-06-04 22:32:23 +00:00
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2017-06-06 13:03:09 +00:00
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uint16_t refresh = 0;
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2017-06-05 13:38:49 +00:00
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uint16_t address = cycle.address ? *cycle.address : 0;
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2017-06-04 22:32:23 +00:00
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switch(cycle.operation) {
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case CPU::Z80::BusOperation::Output:
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2017-06-11 20:42:49 +00:00
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set_vsync(false);
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line_counter_ = 0;
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2017-06-04 22:32:23 +00:00
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break;
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2017-06-06 13:25:18 +00:00
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case CPU::Z80::BusOperation::Input: {
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uint8_t value = 0xff;
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2017-06-06 14:13:32 +00:00
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if(!(address&1)) {
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2017-06-05 01:54:55 +00:00
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set_vsync(true);
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2017-06-06 13:25:18 +00:00
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uint16_t mask = 0x100;
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for(int c = 0; c < 8; c++) {
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if(!(address & mask)) value &= key_states_[c];
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mask <<= 1;
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}
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2017-06-06 14:13:32 +00:00
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2017-06-06 22:38:05 +00:00
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value &= ~(tape_player_.get_input() ? 0x00 : 0x80);
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2017-06-04 22:32:23 +00:00
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}
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2017-06-06 13:25:18 +00:00
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*cycle.value = value;
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} break;
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2017-06-04 22:32:23 +00:00
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case CPU::Z80::BusOperation::Interrupt:
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2017-06-05 01:54:55 +00:00
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set_hsync(true);
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2017-06-06 12:55:07 +00:00
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line_counter_ = (line_counter_ + 1) & 7;
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2017-06-04 22:32:23 +00:00
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*cycle.value = 0xff;
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break;
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case CPU::Z80::BusOperation::ReadOpcode:
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2017-06-05 01:54:55 +00:00
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set_hsync(false);
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2017-06-11 20:42:49 +00:00
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// The ZX80 and 81 signal an interrupt while refresh is active and bit 6 of the refresh
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// address is low. The Z80 signals a refresh, providing the refresh address during the
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// final two cycles of an opcode fetch. Therefore communicate a transient signalling
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// of the IRQ line if necessary.
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2017-06-06 13:03:09 +00:00
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refresh = get_value_of_register(CPU::Z80::Register::Refresh);
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2017-06-11 17:32:20 +00:00
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set_interrupt_line(!(refresh & 0x40), -2);
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2017-06-11 20:42:49 +00:00
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set_interrupt_line(false);
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// Check for use of the fast tape hack.
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if(address == tape_trap_address_) { // TODO: && fast_tape_hack_enabled_
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Storage::Tape::ZX8081::Parser parser;
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int next_byte = parser.get_next_byte(tape_player_.get_tape());
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if(next_byte != -1) {
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uint16_t hl = get_value_of_register(CPU::Z80::Register::HL);
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ram_[hl & 1023] = (uint8_t)next_byte;
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*cycle.value = 0x00;
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2017-06-11 21:28:47 +00:00
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set_value_of_register(CPU::Z80::Register::ProgramCounter, tape_return_address_ - 1);
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2017-06-11 20:42:49 +00:00
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return 0;
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}
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}
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2017-06-04 22:32:23 +00:00
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case CPU::Z80::BusOperation::Read:
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2017-06-05 13:38:49 +00:00
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if((address & 0xc000) == 0x0000) *cycle.value = rom_[address & (rom_.size() - 1)];
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else if((address & 0x4000) == 0x4000) {
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uint8_t value = ram_[address & 1023];
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if(address&0x8000 && !(value & 0x40) && cycle.operation == CPU::Z80::BusOperation::ReadOpcode && !get_halt_line()) {
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2017-06-06 13:03:09 +00:00
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size_t char_address = (size_t)((refresh & 0xff00) | ((value & 0x3f) << 3) | line_counter_);
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2017-06-06 12:55:07 +00:00
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if((char_address & 0xc000) == 0x0000) {
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2017-06-06 13:03:09 +00:00
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uint8_t mask = (value & 0x80) ? 0x00 : 0xff;
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2017-06-06 12:55:07 +00:00
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value = rom_[char_address & (rom_.size() - 1)] ^ mask;
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}
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2017-06-06 21:53:23 +00:00
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video_->output_byte(value);
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2017-06-04 22:32:23 +00:00
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*cycle.value = 0;
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2017-06-05 14:36:07 +00:00
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} else *cycle.value = value;
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2017-06-04 22:32:23 +00:00
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}
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break;
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case CPU::Z80::BusOperation::Write:
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2017-06-05 13:38:49 +00:00
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if((address & 0x4000) == 0x4000) ram_[address & 1023] = *cycle.value;
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2017-06-04 22:32:23 +00:00
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break;
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default: break;
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}
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2017-06-04 21:55:19 +00:00
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return 0;
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}
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2017-06-04 22:08:35 +00:00
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void Machine::flush() {
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2017-06-06 21:53:23 +00:00
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video_->flush();
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}
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void Machine::setup_output(float aspect_ratio) {
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video_.reset(new Video);
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2017-06-04 22:08:35 +00:00
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}
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2017-06-04 21:55:19 +00:00
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void Machine::close_output() {
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video_.reset();
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2017-06-04 21:55:19 +00:00
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}
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std::shared_ptr<Outputs::CRT::CRT> Machine::get_crt() {
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2017-06-06 21:53:23 +00:00
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return video_->get_crt();
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2017-06-04 21:55:19 +00:00
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}
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std::shared_ptr<Outputs::Speaker> Machine::get_speaker() {
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return nullptr;
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}
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void Machine::run_for_cycles(int number_of_cycles) {
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2017-06-04 22:37:13 +00:00
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CPU::Z80::Processor<Machine>::run_for_cycles(number_of_cycles);
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2017-06-04 21:55:19 +00:00
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}
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void Machine::configure_as_target(const StaticAnalyser::Target &target) {
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2017-06-06 22:16:27 +00:00
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// TODO: pay attention to the target; it can't currently specify a ZX81
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// so assume a ZX80 if we got here.
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2017-06-11 20:42:49 +00:00
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if(true) {
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rom_ = zx80_rom_;
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tape_trap_address_ = 0x220;
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tape_return_address_ = 0x248;
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} else {
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rom_ = zx81_rom_;
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tape_trap_address_ = 0x37c;
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tape_return_address_ = 0x380;
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}
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2017-06-06 14:13:32 +00:00
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if(target.tapes.size()) {
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tape_player_.set_tape(target.tapes.front());
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}
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2017-06-04 21:55:19 +00:00
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}
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2017-06-04 22:08:35 +00:00
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void Machine::set_rom(ROMType type, std::vector<uint8_t> data) {
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switch(type) {
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case ZX80: zx80_rom_ = data; break;
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case ZX81: zx81_rom_ = data; break;
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}
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}
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2017-06-04 22:32:23 +00:00
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#pragma mark - Video
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2017-06-05 01:54:55 +00:00
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void Machine::set_vsync(bool sync) {
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vsync_ = sync;
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2017-06-05 14:47:42 +00:00
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update_sync();
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2017-06-05 01:54:55 +00:00
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}
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void Machine::set_hsync(bool sync) {
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hsync_ = sync;
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2017-06-05 14:47:42 +00:00
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update_sync();
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}
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void Machine::update_sync() {
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2017-06-06 21:53:23 +00:00
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video_->set_sync(vsync_ || hsync_);
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2017-06-06 12:59:00 +00:00
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}
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2017-06-06 13:25:18 +00:00
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#pragma mark - Keyboard
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void Machine::set_key_state(uint16_t key, bool isPressed) {
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if(isPressed)
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key_states_[key >> 8] &= (uint8_t)(~key);
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else
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key_states_[key >> 8] |= (uint8_t)key;
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}
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void Machine::clear_all_keys() {
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memset(key_states_, 0xff, 8);
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}
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