6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-05 10:28:58 +00:00
Code Issues Projects Releases Wiki Activity
2e9065b34c
CLK/InstructionSets/M50740/Executor.cpp

832 lines
25 KiB
C++
Raw Normal View History

Steps gingerly towards execution.
2021-01-17 01:51:02 +00:00
//
// Executor.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/1/21.
// Copyright © 2021 Thomas Harte. All rights reserved.
//
#include "Executor.hpp"
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 21:59:49 +00:00
#include <algorithm>
Adds missing #include.
2021-01-18 01:56:22 +00:00
#include <cassert>
Succeeds at executing a single instruction.
2021-01-19 01:16:01 +00:00
#include <cstring>
Adds missing #include.
2021-01-18 01:56:22 +00:00
Edges towards implementing an ADB device.
2021-02-13 02:50:24 +00:00
#include "../../Machines/Utility/MemoryFuzzer.hpp"
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
#define LOG_PREFIX "[M50740] "
#include "../../Outputs/Log.hpp"
Steps gingerly towards execution.
2021-01-17 01:51:02 +00:00
using namespace InstructionSet::M50740;
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
namespace {
constexpr int port_remap[] = {0, 1, 2, 0, 3};
}
Executor::Executor(PortHandler &port_handler) : port_handler_(port_handler) {
Bends to using 8-bit lookups for M50740 instructions.
2021-01-18 01:03:36 +00:00
// Cut down the list of all generated performers to those the processor actually uses, and install that
// for future referencing by action_for.
Decoder decoder;
for(size_t c = 0; c < 256; c++) {
const auto instruction = decoder.instrucion_for_opcode(uint8_t(c));
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 21:59:49 +00:00
// Treat invalid as NOP, because I've got to do _something_.
if(instruction.operation == Operation::Invalid) {
performers_[c] = performer_lookup_.performer(Operation::NOP, instruction.addressing_mode);
} else {
performers_[c] = performer_lookup_.performer(instruction.operation, instruction.addressing_mode);
}
Bends to using 8-bit lookups for M50740 instructions.
2021-01-18 01:03:36 +00:00
}
Edges towards implementing an ADB device.
2021-02-13 02:50:24 +00:00
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 22:53:40 +00:00
// Fuzz RAM; then set anything that may be replaced by ROM to FF.
Edges towards implementing an ADB device.
2021-02-13 02:50:24 +00:00
Memory::Fuzz(memory_);
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 22:53:40 +00:00
memset(&memory_[0x100], 0xff, memory_.size() - 0x100);
Steps gingerly towards execution.
2021-01-17 01:51:02 +00:00
}
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 21:59:49 +00:00
void Executor::set_rom(const std::vector<uint8_t> &rom) {
// Copy into place, and reset.
const auto length = std::min(size_t(0x1000), rom.size());
memcpy(&memory_[0x2000 - length], rom.data(), length);
reset();
Starts formalising end conditions.
2021-01-22 03:36:44 +00:00
}
void Executor::run_for(Cycles cycles) {
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
// The incoming clock is divided by four; the local cycles_ count
// ensures that fractional parts are kept track of.
Ensures ADB microcontroller is clocked. And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
2021-01-24 03:55:12 +00:00
cycles_ += cycles;
CachingExecutor::run_for(cycles_.divide(Cycles(4)).as<int>());
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 21:59:49 +00:00
}
void Executor::reset() {
// Just jump to the reset vector.
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
set_program_counter(uint16_t(memory_[0x1ffe] | (memory_[0x1fff] << 8)));
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 21:59:49 +00:00
}
Makes first effort to wire up the ADB vertical blank input. However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-15 03:20:58 +00:00
void Executor::set_interrupt_line(bool line) {
// Super hack: interrupt now, if permitted. Otherwise do nothing.
// So this will fail to catch enabling of interrupts while the line
// is active, amongst other things.
if(interrupt_line_ != line) {
interrupt_line_ = line;
// TODO: verify interrupt connection. Externally, but stubbed off here.
// if(!interrupt_disable_ && line) {
// perform_interrupt<false>(0x1ff4);
// }
}
}
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
uint8_t Executor::read(uint16_t address) {
address &= 0x1fff;
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 22:53:40 +00:00
// Deal with RAM and ROM accesses quickly.
if(address < 0x60 || address >= 0x100) return memory_[address];
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
port_handler_.run_ports_for(cycles_since_port_handler_.flush<Cycles>());
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
switch(address) {
Rips out my high-level ADB microcontroller protocol implementation. Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 22:53:27 +00:00
default:
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
LOG("Unrecognised read from " << PADHEX(4) << address);
Rips out my high-level ADB microcontroller protocol implementation. Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 22:53:27 +00:00
return 0xff;
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
// "Port R"; sixteen four-bit ports
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
LOG("Unimplemented Port R read from " << PADHEX(4) << address);
Makes first effort to wire up the ADB vertical blank input. However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-15 03:20:58 +00:00
return 0x00;
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
// Ports P0–P3.
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
case 0xe0: case 0xe2:
Implements direction registers.
2021-01-29 02:06:11 +00:00
case 0xe4: case 0xe8: {
const int port = port_remap[(address - 0xe0) >> 1];
const uint8_t input = port_handler_.get_port_input(port);
// In the direction registers, a 0 indicates input, a 1 indicates output.
return (input &~ port_directions_[port]) | (port_outputs_[port] & port_directions_[port]);
}
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
case 0xe1: case 0xe3:
case 0xe5: case 0xe9:
Rips out my high-level ADB microcontroller protocol implementation. Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 22:53:27 +00:00
return port_directions_[port_remap[(address - 0xe0) >> 1]];
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
// Timers.
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
case 0xf9: return prescalers_[0].value;
case 0xfa: return timers_[0].value;
case 0xfb: return timers_[1].value;
case 0xfc: return prescalers_[1].value;
case 0xfd: return timers_[2].value;
case 0xfe: return interrupt_control_;
case 0xff: return timer_control_;
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
}
}
Provide a more convincing version of port output.
2021-02-08 23:14:08 +00:00
void Executor::set_port_output(int port) {
// Force 'output' to a 1 anywhere that a bit is set as input.
port_handler_.set_port_output(port, port_outputs_[port] | ~port_directions_[port]);
}
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
void Executor::write(uint16_t address, uint8_t value) {
address &= 0x1fff;
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
// RAM writes are easy.
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
if(address < 0x60) {
memory_[address] = value;
return;
}
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 22:53:40 +00:00
// ROM 'writes' are almost as easy (albeit unexpected).
if(address >= 0x100) {
LOG("Attempted ROM write of " << PADHEX(2) << value << " to " << PADHEX(4) << address);
return;
}
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
// Push time to the port handler.
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
port_handler_.run_ports_for(cycles_since_port_handler_.flush<Cycles>());
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
switch(address) {
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
default:
LOG("Unrecognised write of " << PADHEX(2) << value << " to " << PADHEX(4) << address);
break;
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
// "Port R"; sixteen four-bit ports
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
LOG("Unimplemented Port R write of " << PADHEX(2) << value << " from " << PADHEX(4) << address);
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
break;
// Ports P0–P3.
case 0xe0: case 0xe2:
Implements direction registers.
2021-01-29 02:06:11 +00:00
case 0xe4: case 0xe8: {
const int port = port_remap[(address - 0xe0) >> 1];
port_outputs_[port] = value;
Provide a more convincing version of port output.
2021-02-08 23:14:08 +00:00
set_port_output(port);
Implements direction registers.
2021-01-29 02:06:11 +00:00
}
Provide a more convincing version of port output.
2021-02-08 23:14:08 +00:00
break;
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
case 0xe1: case 0xe3:
Provide a more convincing version of port output.
2021-02-08 23:14:08 +00:00
case 0xe5: case 0xe9: {
const int port = port_remap[(address - 0xe0) >> 1];
port_directions_[port] = value;
set_port_output(port);
} break;
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
// Timers.
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
case 0xf9: prescalers_[0].reload_value = value; break;
case 0xfa: timers_[0].reload_value = value; break;
case 0xfb: timers_[1].reload_value = value; break;
case 0xfc: prescalers_[1].reload_value = value; break;
case 0xfd: timers_[2].reload_value = value; break;
case 0xfe: interrupt_control_ = value; break;
case 0xff: timer_control_ = value; break;
Attempts to wire up M50470 and GLU. Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 23:07:05 +00:00
}
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
}
void Executor::push(uint8_t value) {
write(s_, value);
--s_;
}
Gets beyond a prima facie convincing JSR/RET.
2021-01-20 23:21:44 +00:00
uint8_t Executor::pull() {
++s_;
return read(s_);
}
Pushes ahead to what will be my first interaction with the T flag.
2021-01-21 01:27:09 +00:00
void Executor::set_flags(uint8_t flags) {
negative_result_ = flags;
overflow_result_ = uint8_t(flags << 1);
index_mode_ = flags & 0x20;
decimal_mode_ = flags & 0x08;
interrupt_disable_ = flags & 0x04;
zero_result_ = !(flags & 0x02);
carry_flag_ = flags & 0x01;
}
uint8_t Executor::flags() {
return
(negative_result_ & 0x80) |
((overflow_result_ & 0x80) >> 1) |
(index_mode_ ? 0x20 : 0x00) |
(decimal_mode_ ? 0x08 : 0x00) |
interrupt_disable_ |
(zero_result_ ? 0x00 : 0x02) |
carry_flag_;
}
Makes first effort to wire up the ADB vertical blank input. However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-15 03:20:58 +00:00
template<bool is_brk> inline void Executor::perform_interrupt(uint16_t vector) {
Completes M50740 instruction set.
2021-01-22 00:08:38 +00:00
// BRK has an unused operand.
++program_counter_;
push(uint8_t(program_counter_ >> 8));
push(uint8_t(program_counter_ & 0xff));
push(flags() | (is_brk ? 0x10 : 0x00));
Honours interrupt vector.
2021-02-15 20:05:56 +00:00
set_program_counter(uint16_t(memory_[vector] | (memory_[vector+1] << 8)));
Completes M50740 instruction set.
2021-01-22 00:08:38 +00:00
}
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
template <Operation operation, AddressingMode addressing_mode> void Executor::perform() {
Starts formalising end conditions.
2021-01-22 03:36:44 +00:00
// Post cycle cost; this emulation _does not provide accurate timing_.
Posts cycle lengths.
2021-01-24 02:58:52 +00:00
#define TLength(mode, base) case AddressingMode::mode: subtract_duration(base + t_lengths[index_mode_]); break;
#define Length(mode, base) case AddressingMode::mode: subtract_duration(base); break;
switch(operation) {
case Operation::ADC: case Operation::AND: case Operation::CMP: case Operation::EOR:
case Operation::LDA: case Operation::ORA: case Operation::SBC:
{
constexpr int t_lengths[] = {
0,
operation == Operation::LDA ? 2 : (operation == Operation::CMP ? 1 : 3)
};
switch(addressing_mode) {
TLength(XIndirect, 6);
TLength(ZeroPage, 3);
TLength(Immediate, 2);
TLength(Absolute, 4);
TLength(IndirectY, 6);
TLength(ZeroPageX, 4);
TLength(AbsoluteY, 5);
TLength(AbsoluteX, 5);
default: assert(false);
}
} break;
case Operation::ASL: case Operation::DEC: case Operation::INC: case Operation::LSR:
case Operation::ROL: case Operation::ROR:
switch(addressing_mode) {
Length(ZeroPage, 5);
Length(Accumulator, 2);
Length(Absolute, 6);
Length(ZeroPageX, 6);
Length(AbsoluteX, 7);
default: assert(false);
}
break;
case Operation::BBC0: case Operation::BBC1: case Operation::BBC2: case Operation::BBC3:
case Operation::BBC4: case Operation::BBC5: case Operation::BBC6: case Operation::BBC7:
case Operation::BBS0: case Operation::BBS1: case Operation::BBS2: case Operation::BBS3:
case Operation::BBS4: case Operation::BBS5: case Operation::BBS6: case Operation::BBS7:
switch(addressing_mode) {
Length(AccumulatorRelative, 4);
Length(ZeroPageRelative, 5);
default: assert(false);
}
break;
case Operation::BPL: case Operation::BMI: case Operation::BEQ: case Operation::BNE:
case Operation::BCS: case Operation::BCC: case Operation::BVS: case Operation::BVC:
case Operation::INX: case Operation::INY:
subtract_duration(2);
break;
case Operation::CPX: case Operation::CPY: case Operation::BIT: case Operation::LDX:
case Operation::LDY:
switch(addressing_mode) {
Length(Immediate, 2);
Length(ZeroPage, 3);
Length(Absolute, 4);
Length(ZeroPageX, 4);
Length(ZeroPageY, 4);
Length(AbsoluteX, 5);
Length(AbsoluteY, 5);
default: assert(false);
}
break;
case Operation::BRA: subtract_duration(4); break;
case Operation::BRK: subtract_duration(7); break;
case Operation::CLB0: case Operation::CLB1: case Operation::CLB2: case Operation::CLB3:
case Operation::CLB4: case Operation::CLB5: case Operation::CLB6: case Operation::CLB7:
case Operation::SEB0: case Operation::SEB1: case Operation::SEB2: case Operation::SEB3:
case Operation::SEB4: case Operation::SEB5: case Operation::SEB6: case Operation::SEB7:
switch(addressing_mode) {
Length(Accumulator, 2);
Length(ZeroPage, 5);
default: assert(false);
}
break;
case Operation::CLC: case Operation::CLD: case Operation::CLT: case Operation::CLV:
case Operation::CLI:
case Operation::DEX: case Operation::DEY: case Operation::FST: case Operation::NOP:
case Operation::SEC: case Operation::SED: case Operation::SEI: case Operation::SET:
case Operation::SLW: case Operation::STP: case Operation::TAX: case Operation::TAY:
case Operation::TSX: case Operation::TXA: case Operation::TXS: case Operation::TYA:
subtract_duration(2);
break;
case Operation::COM: subtract_duration(5); break;
case Operation::JMP:
switch(addressing_mode) {
Length(Absolute, 3);
Length(AbsoluteIndirect, 5);
Length(ZeroPageIndirect, 4);
default: assert(false);
}
break;
case Operation::JSR:
switch(addressing_mode) {
Length(ZeroPageIndirect, 7);
Length(Absolute, 6);
Length(SpecialPage, 5);
default: assert(false);
}
break;
case Operation::LDM: subtract_duration(4); break;
case Operation::PHA: case Operation::PHP: case Operation::TST:
subtract_duration(3);
break;
case Operation::PLA: case Operation::PLP:
subtract_duration(4);
break;
case Operation::RRF: subtract_duration(8); break;
case Operation::RTI: subtract_duration(6); break;
case Operation::RTS: subtract_duration(6); break;
case Operation::STA: case Operation::STX: case Operation::STY:
switch(addressing_mode) {
Length(XIndirect, 7);
Length(ZeroPage, 4);
Length(Absolute, 5);
Length(IndirectY, 7);
Length(ZeroPageX, 5);
Length(ZeroPageY, 5);
Length(AbsoluteY, 6);
Length(AbsoluteX, 6);
default: assert(false);
}
break;
default: assert(false);
}
Starts formalising end conditions.
2021-01-22 03:36:44 +00:00
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
// Deal with all modes that don't access memory up here;
// those that access memory will go through a slightly longer
// sequence below that wraps the address and checks whether
// a write is valid [if required].
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
unsigned int address;
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
#define next8() memory_[(program_counter_ + 1) & 0x1fff]
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
#define next16() uint16_t(memory_[(program_counter_ + 1) & 0x1fff] | (memory_[(program_counter_ + 2) & 0x1fff] << 8))
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
// Underlying assumption below: the instruction stream will never
// overlap with IO ports.
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
switch(addressing_mode) {
// Addressing modes with no further memory access.
case AddressingMode::Implied:
perform<operation>(nullptr);
++program_counter_;
return;
case AddressingMode::Accumulator:
perform<operation>(&a_);
++program_counter_;
return;
case AddressingMode::Immediate:
perform<operation>(&next8());
program_counter_ += 2;
return;
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
// Special-purpose addressing modes.
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
case AddressingMode::Relative:
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned(program_counter_ + 1 + size(addressing_mode) + int8_t(next8()));
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
break;
case AddressingMode::SpecialPage: address = 0x1f00 | next8(); break;
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
case AddressingMode::ImmediateZeroPage:
// LDM only...
write(memory_[(program_counter_+2)&0x1fff], memory_[(program_counter_+1)&0x1fff]);
program_counter_ += 1 + size(addressing_mode);
return;
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
Takes a swing at BBC, BBS.
2021-01-21 01:52:04 +00:00
case AddressingMode::AccumulatorRelative:
case AddressingMode::ZeroPageRelative: {
// Order of bytes is: (i) zero page address; (ii) relative jump.
uint8_t value;
if constexpr (addressing_mode == AddressingMode::AccumulatorRelative) {
value = a_;
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned(program_counter_ + 1 + size(addressing_mode) + int8_t(next8()));
Takes a swing at BBC, BBS.
2021-01-21 01:52:04 +00:00
} else {
value = read(next8());
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned(program_counter_ + 1 + size(addressing_mode) + int8_t(memory_[(program_counter_+2)&0x1fff]));
Takes a swing at BBC, BBS.
2021-01-21 01:52:04 +00:00
}
program_counter_ += 1 + size(addressing_mode);
switch(operation) {
case Operation::BBS0: case Operation::BBS1: case Operation::BBS2: case Operation::BBS3:
Attempts to fix BBC. But thereby stops all ADB output.
2021-01-26 03:34:03 +00:00
case Operation::BBS4: case Operation::BBS5: case Operation::BBS6: case Operation::BBS7: {
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
if constexpr (operation >= Operation::BBS0 && operation <= Operation::BBS7) {
Attempts to fix BBC. But thereby stops all ADB output.
2021-01-26 03:34:03 +00:00
constexpr uint8_t mask = 1 << (int(operation) - int(Operation::BBS0));
if(value & mask) {
Posts cycle lengths.
2021-01-24 02:58:52 +00:00
set_program_counter(uint16_t(address));
subtract_duration(2);
}
}
Attempts to fix BBC. But thereby stops all ADB output.
2021-01-26 03:34:03 +00:00
} return;
Takes a swing at BBC, BBS.
2021-01-21 01:52:04 +00:00
case Operation::BBC0: case Operation::BBC1: case Operation::BBC2: case Operation::BBC3:
Attempts to fix BBC. But thereby stops all ADB output.
2021-01-26 03:34:03 +00:00
case Operation::BBC4: case Operation::BBC5: case Operation::BBC6: case Operation::BBC7: {
if constexpr (operation >= Operation::BBC0 && operation <= Operation::BBC7) {
constexpr uint8_t mask = 1 << (int(operation) - int(Operation::BBC0));
if(!(value & mask)) {
Posts cycle lengths.
2021-01-24 02:58:52 +00:00
set_program_counter(uint16_t(address));
subtract_duration(2);
}
}
Attempts to fix BBC. But thereby stops all ADB output.
2021-01-26 03:34:03 +00:00
} return;
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
default: assert(false);
Takes a swing at BBC, BBS.
2021-01-21 01:52:04 +00:00
}
} break;
Continues walking very slowly towards cached execution.
2021-01-18 16:20:45 +00:00
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
// Addressing modes with a memory access.
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
case AddressingMode::Absolute: address = next16(); break;
case AddressingMode::AbsoluteX: address = next16() + x_; break;
case AddressingMode::AbsoluteY: address = next16() + y_; break;
case AddressingMode::ZeroPage: address = next8(); break;
case AddressingMode::ZeroPageX: address = (next8() + x_) & 0xff; break;
Starts formalising end conditions.
2021-01-22 03:36:44 +00:00
case AddressingMode::ZeroPageY: address = (next8() + y_) & 0xff; break;
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
case AddressingMode::ZeroPageIndirect:
address = next8();
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned(memory_[address] | (memory_[(address + 1) & 0xff] << 8));
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
break;
case AddressingMode::XIndirect:
address = (next8() + x_) & 0xff;
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned(memory_[address] | (memory_[(address + 1)&0xff] << 8));
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
break;
case AddressingMode::IndirectY:
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
address = unsigned((memory_[next8()] | (memory_[(next8()+1)&0xff] << 8)) + y_);
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
break;
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
case AddressingMode::AbsoluteIndirect:
address = next16();
Makes first effort to wire up the ADB vertical blank input. However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-15 03:20:58 +00:00
address = unsigned(memory_[address & 0x1fff] | (memory_[(address + 1) & 0x1fff] << 8));
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
break;
default:
assert(false);
}
#undef next16
#undef next8
Takes a run at most of the remaining addressing modes.
2021-01-18 02:52:16 +00:00
program_counter_ += 1 + size(addressing_mode);
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
// Check for a branch; those don't go through the memory accesses below.
switch(operation) {
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
case Operation::BRA: case Operation::JMP:
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
set_program_counter(uint16_t(address));
return;
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
case Operation::JSR: {
Rips out my high-level ADB microcontroller protocol implementation. Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 22:53:27 +00:00
// Push one less than the actual return address.
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
const auto return_address = program_counter_ - 1;
push(uint8_t(return_address >> 8));
push(uint8_t(return_address & 0xff));
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
set_program_counter(uint16_t(address));
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
} return;
Posts cycle lengths.
2021-01-24 02:58:52 +00:00
#define Bcc(c) if(c) { set_program_counter(uint16_t(address)); subtract_duration(2); } return
case Operation::BPL: Bcc(!(negative_result_&0x80));
case Operation::BMI: Bcc(negative_result_&0x80);
case Operation::BEQ: Bcc(!zero_result_);
case Operation::BNE: Bcc(zero_result_);
case Operation::BCS: Bcc(carry_flag_);
case Operation::BCC: Bcc(!carry_flag_);
case Operation::BVS: Bcc(overflow_result_ & 0x80);
case Operation::BVC: Bcc(!(overflow_result_ & 0x80));
#undef Bcc
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
default: break;
}
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
assert(access_type(operation) != AccessType::None);
if constexpr(access_type(operation) == AccessType::Read) {
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
uint8_t source = read(uint16_t(address));
perform<operation>(&source);
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
return;
}
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
uint8_t value;
if constexpr(access_type(operation) == AccessType::ReadModifyWrite) {
value = read(uint16_t(address));
} else {
value = 0xff;
}
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
perform<operation>(&value);
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
write(uint16_t(address), value);
Steps gingerly towards execution.
2021-01-17 01:51:02 +00:00
}
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-18 01:53:11 +00:00
template <Operation operation> void Executor::perform(uint8_t *operand [[maybe_unused]]) {
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
#define set_nz(a) negative_result_ = zero_result_ = (a)
Succeeds at executing a single instruction.
2021-01-19 01:16:01 +00:00
switch(operation) {
Corrects index-mode CMP, LDA.
2021-01-21 02:32:46 +00:00
case Operation::LDA:
if(index_mode_) {
write(x_, *operand);
set_nz(*operand);
} else {
set_nz(a_ = *operand);
}
break;
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
case Operation::LDX: set_nz(x_ = *operand); break;
case Operation::LDY: set_nz(y_ = *operand); break;
Succeeds at executing a single instruction.
2021-01-19 01:16:01 +00:00
case Operation::STA: *operand = a_; break;
case Operation::STX: *operand = x_; break;
case Operation::STY: *operand = y_; break;
Corrects immediate instruction length, muddles through to having to parse a second program segment. Albeit with JSR not yet properly implemented.
2021-01-20 03:12:18 +00:00
case Operation::TXA: set_nz(a_ = x_); break;
case Operation::TYA: set_nz(a_ = y_); break;
case Operation::TXS: s_ = x_; break;
case Operation::TAX: set_nz(x_ = a_); break;
case Operation::TAY: set_nz(y_ = a_); break;
case Operation::TSX: set_nz(x_ = s_); break;
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
case Operation::SEB0: case Operation::SEB1: case Operation::SEB2: case Operation::SEB3:
case Operation::SEB4: case Operation::SEB5: case Operation::SEB6: case Operation::SEB7:
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
if constexpr(operation >= Operation::SEB0 && operation <= Operation::SEB7) {
*operand |= 1 << (int(operation) - int(Operation::SEB0));
}
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
break;
case Operation::CLB0: case Operation::CLB1: case Operation::CLB2: case Operation::CLB3:
case Operation::CLB4: case Operation::CLB5: case Operation::CLB6: case Operation::CLB7:
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-25 03:30:42 +00:00
if constexpr(operation >= Operation::CLB0 && operation <= Operation::CLB7) {
*operand &= ~(1 << (int(operation) - int(Operation::CLB0)));
}
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
break;
case Operation::CLI: interrupt_disable_ = 0x00; break;
Pushes ahead to what will be my first interaction with the T flag.
2021-01-21 01:27:09 +00:00
case Operation::SEI: interrupt_disable_ = 0x04; break;
Adds enough flags seemingly to reach an ASL.
2021-01-20 02:54:15 +00:00
case Operation::CLT: index_mode_ = false; break;
case Operation::SET: index_mode_ = true; break;
case Operation::CLD: decimal_mode_ = false; break;
case Operation::SED: decimal_mode_ = true; break;
Corrects RTS, adds the remainder of the direct flag manipulations.
2021-01-21 01:16:55 +00:00
case Operation::CLC: carry_flag_ = 0; break;
case Operation::SEC: carry_flag_ = 1; break;
case Operation::CLV: overflow_result_ = 0; break;
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
case Operation::DEX: --x_; set_nz(x_); break;
case Operation::INX: ++x_; set_nz(x_); break;
case Operation::DEY: --y_; set_nz(y_); break;
case Operation::INY: ++y_; set_nz(y_); break;
case Operation::DEC: --*operand; set_nz(*operand); break;
case Operation::INC: ++*operand; set_nz(*operand); break;
Gets beyond a prima facie convincing JSR/RET.
2021-01-20 23:21:44 +00:00
case Operation::RTS: {
uint16_t target = pull();
target |= pull() << 8;
Corrects RTS, adds the remainder of the direct flag manipulations.
2021-01-21 01:16:55 +00:00
set_program_counter(target+1);
--program_counter_; // To undo the unavoidable increment
// after exiting from here.
Gets beyond a prima facie convincing JSR/RET.
2021-01-20 23:21:44 +00:00
} break;
Pushes ahead to what will be my first interaction with the T flag.
2021-01-21 01:27:09 +00:00
case Operation::RTI: {
set_flags(pull());
uint16_t target = pull();
target |= pull() << 8;
set_program_counter(target);
--program_counter_; // To undo the unavoidable increment
// after exiting from here.
} break;
Completes M50740 instruction set.
2021-01-22 00:08:38 +00:00
case Operation::BRK:
Makes first effort to wire up the ADB vertical blank input. However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-15 03:20:58 +00:00
perform_interrupt<true>(0x1ff4);
Completes M50740 instruction set.
2021-01-22 00:08:38 +00:00
--program_counter_; // To undo the unavoidable increment
// after exiting from here.
break;
case Operation::STP: set_is_stopped(true); break;
Knocks off the low-hanging instruction fruit.
2021-01-21 01:41:35 +00:00
case Operation::COM: set_nz(*operand ^= 0xff); break;
case Operation::FST: case Operation::SLW: case Operation::NOP:
// TODO: communicate FST and SLW onwards, I imagine. Find out what they interface with.
break;
case Operation::PHA: push(a_); break;
case Operation::PHP: push(flags()); break;
case Operation::PLA: set_nz(a_ = pull()); break;
case Operation::PLP: set_flags(pull()); break;
Pushes ahead to what will be my first interaction with the T flag.
2021-01-21 01:27:09 +00:00
Implements shifts and rotates.
2021-01-21 02:39:13 +00:00
case Operation::ASL:
carry_flag_ = *operand >> 7;
*operand <<= 1;
set_nz(*operand);
break;
case Operation::LSR:
carry_flag_ = *operand & 1;
*operand >>= 1;
set_nz(*operand);
break;
case Operation::ROL: {
const uint8_t temp8 = uint8_t((*operand << 1) | carry_flag_);
carry_flag_ = *operand >> 7;
set_nz(*operand = temp8);
} break;
case Operation::ROR: {
const uint8_t temp8 = uint8_t((*operand >> 1) | (carry_flag_ << 7));
carry_flag_ = *operand & 1;
set_nz(*operand = temp8);
} break;
case Operation::RRF:
*operand = uint8_t((*operand >> 4) | (*operand << 4));
break;
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
Adds BIT.
2021-01-21 02:41:43 +00:00
case Operation::BIT:
zero_result_ = *operand & a_;
negative_result_ = *operand;
overflow_result_ = uint8_t(*operand << 1);
break;
Starts formalising end conditions.
2021-01-22 03:36:44 +00:00
case Operation::TST:
set_nz(*operand);
break;
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
/*
Operations affected by the index mode flag: ADC, AND, CMP, EOR, LDA, ORA, and SBC.
*/
#define index(op) \
if(index_mode_) { \
uint8_t t = read(x_); \
op(t); \
write(x_, t); \
} else { \
op(a_); \
}
Adds a list of missing instructions. Not looking too bad; subject to not yet having a strategy for interrupts, timing, nothing yet implemented for timers, IO ports...
2021-01-21 01:37:35 +00:00
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
#define op_ora(x) set_nz(x |= *operand)
#define op_and(x) set_nz(x &= *operand)
#define op_eor(x) set_nz(x ^= *operand)
case Operation::ORA: index(op_ora); break;
case Operation::AND: index(op_and); break;
case Operation::EOR: index(op_eor); break;
#undef op_eor
#undef op_and
#undef op_ora
Implements ADC and SBC.
2021-01-21 23:53:24 +00:00
#undef index
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
#define op_cmp(x) { \
const uint16_t temp16 = x - *operand; \
set_nz(uint8_t(temp16)); \
carry_flag_ = (~temp16 >> 8)&1; \
}
Corrects index-mode CMP, LDA.
2021-01-21 02:32:46 +00:00
case Operation::CMP:
if(index_mode_) {
op_cmp(read(x_));
} else {
op_cmp(a_);
}
break;
Seemingly advances to the first indefinite loop.
2021-01-21 02:18:52 +00:00
case Operation::CPX: op_cmp(x_); break;
case Operation::CPY: op_cmp(y_); break;
#undef op_cmp
Implements ADC and SBC.
2021-01-21 23:53:24 +00:00
case Operation::SBC:
case Operation::ADC: {
const uint8_t a = index_mode_ ? read(x_) : a_;
if(decimal_mode_) {
if(operation == Operation::ADC) {
uint16_t partials = 0;
int result = carry_flag_;
#define nibble(mask, limit, adjustment, carry) \
result += (a & mask) + (*operand & mask); \
partials += result & mask; \
if(result >= limit) result = ((result + (adjustment)) & (carry - 1)) + carry;
nibble(0x000f, 0x000a, 0x0006, 0x00010);
nibble(0x00f0, 0x00a0, 0x0060, 0x00100);
#undef nibble
overflow_result_ = uint8_t((partials ^ a) & (partials ^ *operand));
set_nz(uint8_t(result));
carry_flag_ = (result >> 8) & 1;
} else {
unsigned int result = 0;
unsigned int borrow = carry_flag_ ^ 1;
const uint16_t decimal_result = uint16_t(a - *operand - borrow);
#define nibble(mask, adjustment, carry) \
result += (a & mask) - (*operand & mask) - borrow; \
if(result > mask) result -= adjustment; \
borrow = (result > mask) ? carry : 0; \
result &= (carry - 1);
nibble(0x000f, 0x0006, 0x00010);
nibble(0x00f0, 0x0060, 0x00100);
#undef nibble
overflow_result_ = uint8_t((decimal_result ^ a) & (~decimal_result ^ *operand));
set_nz(uint8_t(result));
carry_flag_ = ((borrow >> 8)&1)^1;
}
} else {
int result;
if(operation == Operation::ADC) {
result = int(a + *operand + carry_flag_);
overflow_result_ = uint8_t((result ^ a) & (result ^ *operand));
} else {
result = int(a + ~*operand + carry_flag_);
overflow_result_ = uint8_t((result ^ a) & (result ^ ~*operand));
}
set_nz(uint8_t(result));
carry_flag_ = (result >> 8) & 1;
}
if(index_mode_) {
write(x_, a);
} else {
a_ = a;
}
} break;
Pushes ahead to what will be my first interaction with the T flag.
2021-01-21 01:27:09 +00:00
Gets as far as executing a first loop.
2021-01-20 23:15:24 +00:00
/*
Already removed from the instruction stream:
* all branches and jumps;
* LDM.
*/
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
default:
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-11 02:46:56 +00:00
LOG("Unimplemented operation: " << operation);
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
assert(false);
Succeeds at executing a single instruction.
2021-01-19 01:16:01 +00:00
}
Stops trying to force bit ID into the addressing mode.
2021-01-20 02:51:01 +00:00
#undef set_nz
Succeeds at executing a single instruction.
2021-01-19 01:16:01 +00:00
}
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
inline void Executor::subtract_duration(int duration) {
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
// Pass along.
CachingExecutor::subtract_duration(duration);
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
// Update count for potential port accesses.
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
cycles_since_port_handler_ += Cycles(duration);
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
Sets sensible 'reset' values.
2021-02-08 02:53:57 +00:00
// Update timer 1 and 2 prescaler.
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
constexpr int t12_divider = 4; // A divide by 4 has already been applied before counting instruction lengths; therefore
// this additional divide by 4 produces the correct net divide by 16.
Sets sensible 'reset' values.
2021-02-08 02:53:57 +00:00
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
timer_divider_ += duration;
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
const int t12_ticks = update_timer(prescalers_[0], timer_divider_ / t12_divider);
timer_divider_ &= (t12_divider-1);
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
// Update timers 1 and 2. TODO: interrupts (elsewhere?).
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
if(update_timer(timers_[0], t12_ticks)) interrupt_control_ |= 0x20;
if(update_timer(timers_[1], t12_ticks)) interrupt_control_ |= 0x08;
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
// If timer X is disabled, stop.
if(timer_control_&0x20) {
return;
}
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
// Update timer X prescaler.
switch(timer_control_ & 0x0c) {
default: {
Slows timer X, to what may or may not be correct.
2021-02-15 21:40:27 +00:00
const int tx_ticks = update_timer(prescalers_[1], t12_ticks); // TODO: don't hard code this. And is this even right?
Add timer X counting. Still no interrupts.
2021-02-15 21:29:25 +00:00
if(update_timer(timers_[2], tx_ticks))
timer_control_ |= 0x80; // TODO: interrupt result of this.
} break;
case 0x04:
LOG("TODO: Timer X; Pulse output mode");
break;
case 0x08:
LOG("TODO: Timer X; Event counter mode");
break;
case 0x0c:
LOG("TODO: Timer X; Pulse width measurement mode");
break;
}
Attempts properly to track ADB bus activity. Output is not yet a valid ADB stream. Work to do.
2021-01-25 22:43:22 +00:00
}
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
inline int Executor::update_timer(Timer &timer, int count) {
Sets sensible 'reset' values.
2021-02-08 02:53:57 +00:00
const int next_value = timer.value - count;
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
if(next_value < 0) {
// Determine how many reloads were required to get above zero.
const int reload_value = timer.reload_value ? timer.reload_value : 256;
Sets sensible 'reset' values.
2021-02-08 02:53:57 +00:00
const int underflow_count = 1 - next_value / reload_value;
Starts to make some effort at timers.
2021-02-07 02:02:44 +00:00
timer.value = uint8_t((next_value % reload_value) + timer.reload_value);
return underflow_count;
}
timer.value = uint8_t(next_value);
return 0;
}
Reference in New Issue Copy Permalink