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CLK/OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm

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Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
//
// Z80ContentionTests.cpp
// Clock SignalTests
//
// Created by Thomas Harte on 7/4/2021.
// Copyright © 2021 Thomas Harte. All rights reserved.
//
#import <XCTest/XCTest.h>
#include "../../../Processors/Z80/Z80.hpp"
namespace {
Introduces failing test for LD [A/I/R], [A/I/R].
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static constexpr uint16_t initial_pc = 0x0000;
static constexpr uint16_t initial_ir = 0xe000;
Advances to 9 source table rows tested out of 37.
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static constexpr uint16_t initial_bc_de_hl = 0xabcd;
Adds failing test for simple (ii+n) tests.
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static constexpr uint16_t initial_ix_iy = 0x3412;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
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struct CapturingZ80: public CPU::Z80::BusHandler {
Starts on two-bus-cycle instructions, correcting validators.
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template <typename Collection> CapturingZ80(const Collection &code) : z80_(*this) {
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
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// Take a copy of the code.
std::copy(code.begin(), code.end(), ram_);
Introduces failing test for LD [A/I/R], [A/I/R].
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code_length_ = uint16_t(code.size());
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
// Skip the three cycles the Z80 spends on a reset, and
// purge them from the record.
run_for(3);
bus_records_.clear();
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
// Set the refresh address to the EE page and set A to 0x80.
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
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z80_.set_value_of_register(CPU::Z80::Register::I, 0xe0);
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
z80_.set_value_of_register(CPU::Z80::Register::A, 0x80);
Advances to 9 source table rows tested out of 37.
2021-04-10 00:38:17 +00:00
// Set BC, DE and HL.
z80_.set_value_of_register(CPU::Z80::Register::BC, initial_bc_de_hl);
z80_.set_value_of_register(CPU::Z80::Register::DE, initial_bc_de_hl);
z80_.set_value_of_register(CPU::Z80::Register::HL, initial_bc_de_hl);
Adds failing test for simple (ii+n) tests.
2021-04-10 01:28:35 +00:00
// Set IX and IY.
z80_.set_value_of_register(CPU::Z80::Register::IX, initial_ix_iy);
z80_.set_value_of_register(CPU::Z80::Register::IY, initial_ix_iy);
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
void run_for(int cycles) {
z80_.run_for(HalfCycles(Cycles(cycles)));
Add two further tests, add checking of collected data size for all tests.
2021-04-09 22:32:03 +00:00
XCTAssertEqual(bus_records_.size(), cycles * 2);
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
/// A record of the state of the address bus, MREQ, IOREQ and RFSH lines,
/// upon every clock transition.
struct BusRecord {
uint16_t address = 0xffff;
bool mreq = false, ioreq = false, refresh = false;
};
HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// Log the activity.
Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
2021-04-12 03:01:00 +00:00
const uint8_t *const bus_state = cycle.bus_state();
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
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for(int c = 0; c < cycle.length.as<int>(); c++) {
bus_records_.emplace_back();
// TODO: I think everything tested here should have an address,
// but am currently unsure whether the reset program puts the
// address bus in high impedance, as bus req/ack does.
if(cycle.address) {
bus_records_.back().address = *cycle.address;
}
bus_records_.back().mreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::MREQ;
bus_records_.back().ioreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::IOREQ;
bus_records_.back().refresh = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::RFSH;
}
// Provide only reads.
if(
cycle.operation == CPU::Z80::PartialMachineCycle::Read ||
cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode
) {
*cycle.value = ram_[*cycle.address];
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
XCTAssert(cycle.operation != CPU::Z80::PartialMachineCycle::ReadOpcode || *cycle.address < code_length_);
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
return HalfCycles(0);
}
const std::vector<BusRecord> &bus_records() const {
return bus_records_;
}
std::vector<BusRecord> cycle_records() const {
std::vector<BusRecord> cycle_records;
for(size_t c = 0; c < bus_records_.size(); c += 2) {
cycle_records.push_back(bus_records_[c]);
}
return cycle_records;
}
private:
CPU::Z80::Processor<CapturingZ80, false, false> z80_;
uint8_t ram_[65536];
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
uint16_t code_length_ = 0;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
std::vector<BusRecord> bus_records_;
};
}
@interface Z80ContentionTests : XCTestCase
@end
/*!
Tests the Z80's MREQ, IOREQ and address outputs for correlation to those
observed by ZX Spectrum users in the software-side documentation of
contended memory timings.
*/
Starts on two-bus-cycle instructions, correcting validators.
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@implementation Z80ContentionTests
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
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struct ContentionCheck {
uint16_t address;
int length;
};
Restructures, the better to explore errors.
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- (void)compareExpectedContentions:(const std::initializer_list<ContentionCheck> &)contentions found:(const std::vector<ContentionCheck> &)found label:(const char *)label {
XCTAssertEqual(contentions.size(), found.size(), "[%s] found %lu contentions but expected %zu", label, found.size(), contentions.size());
auto contention = contentions.begin();
auto found_contention = found.begin();
while(contention != contentions.end() && found_contention != found.end()) {
XCTAssertEqual(contention->address, found_contention->address, "[%s] mismatched address at step %zu; expected %04x but found %04x", label, contention - contentions.begin(), contention->address, found_contention->address);
XCTAssertEqual(contention->length, found_contention->length, "[%s] mismatched length at step %zu; expected %d but found %d", label, contention - contentions.begin(), contention->length, found_contention->length);
if(contention->address != found_contention->address || contention->length != found_contention->length) {
break;
}
++contention;
++found_contention;
}
}
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
/*!
Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
processed by a Sinclair 48k or 128k ULA.
*/
- (void)validate48Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
// 48[/128]k contention logic: triggered on address alone, _unless_
// MREQ is also active.
const auto bus_records = z80.cycle_records();
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
std::vector<ContentionCheck> found_contentions;
Starts on two-bus-cycle instructions, correcting validators.
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int count = 0;
uint16_t address = bus_records.front().address;
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
for(size_t c = 0; c < bus_records.size(); c++) {
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
++count;
if(
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
c && // i.e. not at front.
!bus_records[c].mreq // i.e. beginning of a new contention.
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
) {
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
found_contentions.emplace_back();
found_contentions.back().address = address;
found_contentions.back().length = count - 1;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
count = 1;
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
address = bus_records[c].address;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
}
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
found_contentions.emplace_back();
found_contentions.back().address = address;
found_contentions.back().length = count;
[self compareExpectedContentions:contentions found:found_contentions label:"48kb"];
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
/*!
Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
processed by an Amstrad gate array.
*/
- (void)validatePlus3Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
// +3 contention logic: triggered by the leading edge of MREQ, sans refresh.
const auto bus_records = z80.bus_records();
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
std::vector<ContentionCheck> found_contentions;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
int count = 0;
uint16_t address = bus_records.front().address;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
for(size_t c = 0; c < bus_records.size(); c += 2) {
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
++count;
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
const bool is_leading_edge = !bus_records[c].mreq && bus_records[c+1].mreq && !bus_records[c].refresh;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
if(
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
c && // i.e. not at front.
is_leading_edge // i.e. beginning of a new contention.
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
) {
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
found_contentions.emplace_back();
found_contentions.back().address = address;
found_contentions.back().length = count - 1;
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
count = 1;
address = bus_records[c].address;
}
}
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
found_contentions.emplace_back();
found_contentions.back().address = address;
found_contentions.back().length = count;
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
Restructures, the better to explore errors.
2021-04-11 01:32:42 +00:00
[self compareExpectedContentions:contentions found:found_contentions label:"+3"];
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
// MARK: - Opcode tests.
Starts on two-bus-cycle instructions, correcting validators.
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- (void)testSimpleOneBytes {
Tests all of the single-byte, no-access opcodes.
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for(uint8_t opcode : {
0x00, // NOP
// LD r, r'.
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6f,
// ALO a, r
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbf,
// INC/DEC r
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0xd9, // EXX
0x08, // EX AF, AF'
0xeb, // EX DE, HL
0x27, // DAA
0x2f, // CPL
0x3f, // CCF
0x37, // SCF
0xf3, // DI
0xfb, // EI
0x17, // RLA
0x1f, // RRA
0x07, // RLCA
0x0f, // RRCA
0xe9, // JP (HL)
}) {
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
Tests all of the single-byte, no-access opcodes.
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z80.run_for(4);
[self validate48Contention:{{initial_pc, 4}} z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}} z80:z80];
}
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
}
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
- (void)testSimpleTwoBytes {
// This group should apparently also include 'NOPD'. Neither I nor any other
// page I could find seems to have heard of 'NOPD'.
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
Fills in the rest of the simple two-byte instructions.
2021-04-09 00:13:52 +00:00
// SRO d (i.e. RLC, RRC, RL, RR, SLA, SRA, SRL and SLL)
Starts on two-bus-cycle instructions, correcting validators.
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{0xcb, 0x00}, {0xcb, 0x01}, {0xcb, 0x02}, {0xcb, 0x03},
{0xcb, 0x04}, {0xcb, 0x05}, {0xcb, 0x07},
Fills in the rest of the simple two-byte instructions.
2021-04-09 00:13:52 +00:00
{0xcb, 0x08}, {0xcb, 0x09}, {0xcb, 0x0a}, {0xcb, 0x0b},
{0xcb, 0x0c}, {0xcb, 0x0d}, {0xcb, 0x0f},
{0xcb, 0x10}, {0xcb, 0x11}, {0xcb, 0x12}, {0xcb, 0x13},
{0xcb, 0x14}, {0xcb, 0x15}, {0xcb, 0x17},
{0xcb, 0x18}, {0xcb, 0x19}, {0xcb, 0x1a}, {0xcb, 0x1b},
{0xcb, 0x1c}, {0xcb, 0x1d}, {0xcb, 0x1f},
{0xcb, 0x20}, {0xcb, 0x21}, {0xcb, 0x22}, {0xcb, 0x23},
{0xcb, 0x24}, {0xcb, 0x25}, {0xcb, 0x27},
{0xcb, 0x28}, {0xcb, 0x29}, {0xcb, 0x2a}, {0xcb, 0x2b},
{0xcb, 0x2c}, {0xcb, 0x2d}, {0xcb, 0x2f},
{0xcb, 0x30}, {0xcb, 0x31}, {0xcb, 0x32}, {0xcb, 0x33},
{0xcb, 0x34}, {0xcb, 0x35}, {0xcb, 0x37},
{0xcb, 0x38}, {0xcb, 0x39}, {0xcb, 0x3a}, {0xcb, 0x3b},
{0xcb, 0x3c}, {0xcb, 0x3d}, {0xcb, 0x3f},
// BIT b, r
{0xcb, 0x40}, {0xcb, 0x41}, {0xcb, 0x42}, {0xcb, 0x43},
{0xcb, 0x44}, {0xcb, 0x45}, {0xcb, 0x47},
{0xcb, 0x48}, {0xcb, 0x49}, {0xcb, 0x4a}, {0xcb, 0x4b},
{0xcb, 0x4c}, {0xcb, 0x4d}, {0xcb, 0x4f},
{0xcb, 0x50}, {0xcb, 0x51}, {0xcb, 0x52}, {0xcb, 0x53},
{0xcb, 0x54}, {0xcb, 0x55}, {0xcb, 0x57},
{0xcb, 0x58}, {0xcb, 0x59}, {0xcb, 0x5a}, {0xcb, 0x5b},
{0xcb, 0x5c}, {0xcb, 0x5d}, {0xcb, 0x5f},
{0xcb, 0x60}, {0xcb, 0x61}, {0xcb, 0x62}, {0xcb, 0x63},
{0xcb, 0x64}, {0xcb, 0x65}, {0xcb, 0x67},
{0xcb, 0x68}, {0xcb, 0x69}, {0xcb, 0x6a}, {0xcb, 0x6b},
{0xcb, 0x6c}, {0xcb, 0x6d}, {0xcb, 0x6f},
{0xcb, 0x70}, {0xcb, 0x71}, {0xcb, 0x72}, {0xcb, 0x73},
{0xcb, 0x74}, {0xcb, 0x75}, {0xcb, 0x77},
{0xcb, 0x78}, {0xcb, 0x79}, {0xcb, 0x7a}, {0xcb, 0x7b},
{0xcb, 0x7c}, {0xcb, 0x7d}, {0xcb, 0x7f},
// RES b, r
{0xcb, 0x80}, {0xcb, 0x81}, {0xcb, 0x82}, {0xcb, 0x83},
{0xcb, 0x84}, {0xcb, 0x85}, {0xcb, 0x87},
{0xcb, 0x88}, {0xcb, 0x89}, {0xcb, 0x8a}, {0xcb, 0x8b},
{0xcb, 0x8c}, {0xcb, 0x8d}, {0xcb, 0x8f},
{0xcb, 0x90}, {0xcb, 0x91}, {0xcb, 0x92}, {0xcb, 0x93},
{0xcb, 0x94}, {0xcb, 0x95}, {0xcb, 0x97},
{0xcb, 0x98}, {0xcb, 0x99}, {0xcb, 0x9a}, {0xcb, 0x9b},
{0xcb, 0x9c}, {0xcb, 0x9d}, {0xcb, 0x9f},
{0xcb, 0xa0}, {0xcb, 0xa1}, {0xcb, 0xa2}, {0xcb, 0xa3},
{0xcb, 0xa4}, {0xcb, 0xa5}, {0xcb, 0xa7},
{0xcb, 0xa8}, {0xcb, 0xa9}, {0xcb, 0xaa}, {0xcb, 0xab},
{0xcb, 0xac}, {0xcb, 0xad}, {0xcb, 0xaf},
{0xcb, 0xb0}, {0xcb, 0xb1}, {0xcb, 0xb2}, {0xcb, 0xb3},
{0xcb, 0xb4}, {0xcb, 0xb5}, {0xcb, 0xb7},
{0xcb, 0xb8}, {0xcb, 0xb9}, {0xcb, 0xba}, {0xcb, 0xbb},
{0xcb, 0xbc}, {0xcb, 0xbd}, {0xcb, 0xbf},
// SET b, r
{0xcb, 0xc0}, {0xcb, 0xc1}, {0xcb, 0xc2}, {0xcb, 0xc3},
{0xcb, 0xc4}, {0xcb, 0xc5}, {0xcb, 0xc7},
{0xcb, 0xc8}, {0xcb, 0xc9}, {0xcb, 0xca}, {0xcb, 0xcb},
{0xcb, 0xcc}, {0xcb, 0xcd}, {0xcb, 0xcf},
{0xcb, 0xc0}, {0xcb, 0xd1}, {0xcb, 0xd2}, {0xcb, 0xd3},
{0xcb, 0xd4}, {0xcb, 0xd5}, {0xcb, 0xd7},
{0xcb, 0xd8}, {0xcb, 0xd9}, {0xcb, 0xda}, {0xcb, 0xdb},
{0xcb, 0xdc}, {0xcb, 0xdd}, {0xcb, 0xdf},
{0xcb, 0xe0}, {0xcb, 0xe1}, {0xcb, 0xe2}, {0xcb, 0xe3},
{0xcb, 0xe4}, {0xcb, 0xe5}, {0xcb, 0xe7},
{0xcb, 0xe8}, {0xcb, 0xe9}, {0xcb, 0xea}, {0xcb, 0xeb},
{0xcb, 0xec}, {0xcb, 0xed}, {0xcb, 0xef},
{0xcb, 0xf0}, {0xcb, 0xf1}, {0xcb, 0xf2}, {0xcb, 0xf3},
{0xcb, 0xf4}, {0xcb, 0xf5}, {0xcb, 0xf7},
{0xcb, 0xf8}, {0xcb, 0xf9}, {0xcb, 0xfa}, {0xcb, 0xfb},
{0xcb, 0xfc}, {0xcb, 0xfd}, {0xcb, 0xff},
// NEG
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
{0xed, 0x44}, {0xed, 0x4c}, {0xed, 0x54}, {0xed, 0x5c},
{0xed, 0x64}, {0xed, 0x6c}, {0xed, 0x74}, {0xed, 0x7c},
Fills in the rest of the simple two-byte instructions.
2021-04-09 00:13:52 +00:00
// IM 0/1/2
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
{0xed, 0x46}, {0xed, 0x4e}, {0xed, 0x56}, {0xed, 0x5e},
{0xed, 0x66}, {0xed, 0x6e}, {0xed, 0x66}, {0xed, 0x6e},
Starts on two-bus-cycle instructions, correcting validators.
2021-04-09 00:01:46 +00:00
}) {
CapturingZ80 z80(sequence);
z80.run_for(8);
[self validate48Contention:{{initial_pc, 4}, {initial_pc+1, 4}} z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 4}} z80:z80];
}
}
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
- (void)testAIR {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
{0xed, 0x57}, // LD A, I
{0xed, 0x5f}, // LD A, R
{0xed, 0x47}, // LD I, A
{0xed, 0x4f}, // LD R, A
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
}) {
CapturingZ80 z80(sequence);
z80.run_for(9);
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-09 02:09:33 +00:00
[self validate48Contention:{{initial_pc, 4}, {initial_pc+1, 4}, {initial_ir+1, 1}} z80:z80];
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-09 00:28:55 +00:00
[self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 5}} z80:z80];
}
}
Adds INC/DEC rr and LD SP, HL tests.
2021-04-09 02:14:53 +00:00
- (void)testINCDEC16 {
for(uint8_t opcode : {
Adds failing ADD hl, dd test.
2021-04-09 02:19:22 +00:00
// INC dd
Adds INC/DEC rr and LD SP, HL tests.
2021-04-09 02:14:53 +00:00
0x03, 0x13, 0x23, 0x33,
Adds failing ADD hl, dd test.
2021-04-09 02:19:22 +00:00
// DEC dd
Adds INC/DEC rr and LD SP, HL tests.
2021-04-09 02:14:53 +00:00
0x0b, 0x1b, 0x2b, 0x3b,
// LD SP, HL
0xf9,
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(6);
[self validate48Contention:{{initial_pc, 4}, {initial_ir, 1}, {initial_ir, 1}} z80:z80];
[self validatePlus3Contention:{{initial_pc, 6}} z80:z80];
}
}
Adds failing ADD hl, dd test.
2021-04-09 02:19:22 +00:00
- (void)testADDHLdd {
for(uint8_t opcode : {
// ADD hl, dd
0x09, 0x19, 0x29, 0x39,
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(11);
[self validate48Contention:{
{initial_pc, 4},
Makes assumption that the address bus just holds its value during an internal operation.
2021-04-10 16:00:53 +00:00
{initial_ir, 1},
{initial_ir, 1},
{initial_ir, 1},
{initial_ir, 1},
{initial_ir, 1},
{initial_ir, 1},
{initial_ir, 1},
Adds failing ADD hl, dd test.
2021-04-09 02:19:22 +00:00
} z80:z80];
[self validatePlus3Contention:{{initial_pc, 11}} z80:z80];
}
}
Adds INC/DEC rr and LD SP, HL tests.
2021-04-09 02:14:53 +00:00
Add two further tests, add checking of collected data size for all tests.
2021-04-09 22:32:03 +00:00
- (void)testADCSBCHLdd {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
// ADC HL, dd
{0xed, 0x4a}, {0xed, 0x5a}, {0xed, 0x6a}, {0xed, 0x7a},
// SBC HL, dd
{0xed, 0x42}, {0xed, 0x52}, {0xed, 0x62}, {0xed, 0x72},
}) {
CapturingZ80 z80(sequence);
z80.run_for(15);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
Makes assumption that the address bus just holds its value during an internal operation.
2021-04-10 16:00:53 +00:00
{initial_ir+1, 1},
{initial_ir+1, 1},
{initial_ir+1, 1},
{initial_ir+1, 1},
{initial_ir+1, 1},
{initial_ir+1, 1},
{initial_ir+1, 1},
Add two further tests, add checking of collected data size for all tests.
2021-04-09 22:32:03 +00:00
} z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 11}} z80:z80];
}
}
- (void)testLDrnALOAn {
for(uint8_t opcode : {
// LD r, n
0x06, 0x0e, 0x16, 0x1e, 0x26, 0x2e, 0x3e,
Advances to 9 source table rows tested out of 37.
2021-04-10 00:38:17 +00:00
0xc6, // ADD A, n
Add two further tests, add checking of collected data size for all tests.
2021-04-09 22:32:03 +00:00
0xce, // ADC A, n
0xde, // SBC A, n
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(7);
[self validate48Contention:{{initial_pc, 4}, {initial_pc+1, 3}} z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 3}} z80:z80];
}
}
Advances to 9 source table rows tested out of 37.
2021-04-10 00:38:17 +00:00
- (void)testLDrind {
for(uint8_t opcode : {
// LD r, (dd)
0x0a, 0x1a,
0x46, 0x4e, 0x56, 0x5e, 0x66, 0x6e, 0x7e, 0x86,
// LD (ss), r
0x02, 0x12,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x77,
// ALO A, (HL)
0x86, 0x8e, 0x96, 0x9e, 0xa6, 0xae, 0xb6, 0xbe
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(7);
[self validate48Contention:{{initial_pc, 4}, {initial_bc_de_hl, 3}} z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}, {initial_bc_de_hl, 3}} z80:z80];
}
}
Adds failing test for simple (ii+n) tests.
2021-04-10 01:28:35 +00:00
- (void)testLDiiPlusn {
constexpr uint8_t offset = 0x10;
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
// LD r, (ii+n)
{0xdd, 0x46, offset}, {0xdd, 0x4e, offset},
{0xdd, 0x56, offset}, {0xdd, 0x5e, offset},
{0xdd, 0x66, offset}, {0xdd, 0x6e, offset},
{0xfd, 0x46, offset}, {0xfd, 0x4e, offset},
{0xfd, 0x56, offset}, {0xfd, 0x5e, offset},
{0xfd, 0x66, offset}, {0xfd, 0x6e, offset},
// LD (ii+n), r
{0xdd, 0x70, offset}, {0xdd, 0x71, offset},
{0xdd, 0x72, offset}, {0xdd, 0x73, offset},
{0xdd, 0x74, offset}, {0xdd, 0x75, offset},
{0xdd, 0x77, offset},
{0xfd, 0x70, offset}, {0xfd, 0x71, offset},
{0xfd, 0x72, offset}, {0xfd, 0x73, offset},
{0xfd, 0x74, offset}, {0xfd, 0x75, offset},
{0xfd, 0x77, offset},
// ALO A, (ii+n)
{0xdd, 0x86, offset}, {0xdd, 0x8e, offset},
{0xdd, 0x96, offset}, {0xdd, 0x9e, offset},
{0xdd, 0xa6, offset}, {0xdd, 0xae, offset},
{0xdd, 0xb6, offset}, {0xdd, 0xbe, offset},
{0xfd, 0x86, offset}, {0xfd, 0x8e, offset},
{0xfd, 0x96, offset}, {0xfd, 0x9e, offset},
{0xfd, 0xa6, offset}, {0xfd, 0xae, offset},
{0xfd, 0xb6, offset}, {0xfd, 0xbe, offset},
}) {
CapturingZ80 z80(sequence);
z80.run_for(19);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+2, 1},
{initial_pc+2, 1},
{initial_pc+2, 1},
{initial_pc+2, 1},
{initial_pc+2, 1},
{initial_ix_iy + offset, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 8},
{initial_ix_iy + offset, 3},
} z80:z80];
}
}
Introduces failing test for bit b, (hl).
2021-04-10 16:04:48 +00:00
- (void)testBITbhl {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
Introduces failing test for BIT b, (ii+n).
2021-04-10 22:00:23 +00:00
{0xcb, 0x46}, {0xcb, 0x4e},
{0xcb, 0x56}, {0xcb, 0x5e},
{0xcb, 0x66}, {0xcb, 0x6e},
{0xcb, 0x76}, {0xcb, 0x7e},
Introduces failing test for bit b, (hl).
2021-04-10 16:04:48 +00:00
}) {
CapturingZ80 z80(sequence);
z80.run_for(12);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_bc_de_hl, 3},
{initial_bc_de_hl, 1},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_bc_de_hl, 4},
} z80:z80];
}
}
Introduces failing test for BIT b, (ii+n).
2021-04-10 22:00:23 +00:00
- (void)testBITbiin {
constexpr uint8_t offset = 0x10;
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
// BIT b, (ix+d)
{0xdd, 0xcb, offset, 0x46}, {0xdd, 0xcb, offset, 0x4e},
{0xdd, 0xcb, offset, 0x56}, {0xdd, 0xcb, offset, 0x5e},
{0xdd, 0xcb, offset, 0x66}, {0xdd, 0xcb, offset, 0x6e},
{0xdd, 0xcb, offset, 0x76}, {0xdd, 0xcb, offset, 0x7e},
// BIT b, (iy+d)
{0xfd, 0xcb, offset, 0x46}, {0xfd, 0xcb, offset, 0x4e},
{0xfd, 0xcb, offset, 0x56}, {0xfd, 0xcb, offset, 0x5e},
{0xfd, 0xcb, offset, 0x66}, {0xfd, 0xcb, offset, 0x6e},
{0xfd, 0xcb, offset, 0x76}, {0xfd, 0xcb, offset, 0x7e},
}) {
CapturingZ80 z80(sequence);
z80.run_for(20);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 3},
{initial_pc+3, 1},
{initial_pc+3, 1},
{initial_ix_iy + offset, 3},
{initial_ix_iy + offset, 1},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 5},
{initial_ix_iy + offset, 4},
} z80:z80];
}
}
Advances to next failing test: `LD (ii+n), n`.
2021-04-12 21:11:58 +00:00
- (void)testLDJPJRnn {
for(uint8_t opcode : {
// LD rr, dd
0x01, 0x11, 0x21, 0x31,
// JP nn, JP cc, nn
0xc2, 0xc3, 0xd2, 0xe2, 0xf2,
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(10);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
} z80:z80];
}
}
- (void)testLDindHLn {
for(uint8_t opcode : {
// LD (HL), n
0x36
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(10);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_bc_de_hl, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_bc_de_hl, 3},
} z80:z80];
}
}
- (void)testLDiiPlusnn {
constexpr uint8_t offset = 0x10;
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
// LD (ii+n), n
{0xdd, 0x36, offset}, {0xfd, 0x36, offset},
}) {
CapturingZ80 z80(sequence);
z80.run_for(19);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 3},
{initial_pc+3, 1},
{initial_pc+3, 1},
{initial_ix_iy + offset, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 5},
{initial_ix_iy + offset, 3},
} z80:z80];
}
}
Reaches the halfway point in tests.
2021-04-12 21:29:03 +00:00
- (void)testLDAind {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
{0x32, 0xcd, 0xab}, // LD (nn), a
{0x3a, 0xcd, 0xab}, // LD a, (nn)
}) {
CapturingZ80 z80(sequence);
z80.run_for(13);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
{0xabcd, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
{0xabcd, 3},
} z80:z80];
}
}
- (void)testLDHLind {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
{0x22, 0xcd, 0xab}, // LD (nn), HL
{0x2a, 0xcd, 0xab}, // LD HL, (nn)
}) {
CapturingZ80 z80(sequence);
z80.run_for(16);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
{0xabcd, 3},
{0xabce, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 3},
{initial_pc+2, 3},
{0xabcd, 3},
{0xabce, 3},
} z80:z80];
}
}
- (void)testLDrrind {
for(const auto &sequence : std::vector<std::vector<uint8_t>>{
{0xed, 0x43, 0xcd, 0xab}, // LD (nn), BC
{0xed, 0x53, 0xcd, 0xab}, // LD (nn), DE
{0xed, 0x63, 0xcd, 0xab}, // LD (nn), HL
{0xed, 0x73, 0xcd, 0xab}, // LD (nn), SP
{0xed, 0x4b, 0xcd, 0xab}, // LD BC, (nn)
{0xed, 0x5b, 0xcd, 0xab}, // LD DE, (nn)
{0xed, 0x6b, 0xcd, 0xab}, // LD HL, (nn)
{0xed, 0x7b, 0xcd, 0xab}, // LD SP, (nn)
}) {
CapturingZ80 z80(sequence);
z80.run_for(20);
[self validate48Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 3},
{0xabcd, 3},
{0xabce, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_pc+1, 4},
{initial_pc+2, 3},
{initial_pc+3, 3},
{0xabcd, 3},
{0xabce, 3},
} z80:z80];
}
}
- (void)testINCDECHL {
for(uint8_t opcode : {
0x34, // INC (HL)
0x35, // DEC (HL)
}) {
const std::initializer_list<uint8_t> opcodes = {opcode};
CapturingZ80 z80(opcodes);
z80.run_for(11);
[self validate48Contention:{
{initial_pc, 4},
{initial_bc_de_hl, 3},
{initial_bc_de_hl, 1},
{initial_bc_de_hl, 3},
} z80:z80];
[self validatePlus3Contention:{
{initial_pc, 4},
{initial_bc_de_hl, 4},
{initial_bc_de_hl, 3},
} z80:z80];
}
}
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-08 01:57:40 +00:00
@end
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