2019-03-09 05:00:23 +00:00
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//
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// 68000Storage.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "../68000.hpp"
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2019-03-13 02:46:31 +00:00
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#include <array>
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2019-03-09 05:00:23 +00:00
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using namespace CPU::MC68000;
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ProcessorStorage::ProcessorStorage() {
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2019-03-13 02:46:31 +00:00
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// Create the exception programs.
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const size_t reset_offset = assemble_program("n- n- n- n- n- nn nF nf nV nv np np");
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2019-03-10 21:27:34 +00:00
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2019-03-13 02:46:31 +00:00
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// Install all necessary access patterns.
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const BusStepCollection bus_steps = assemble_standard_bus_steps();
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2019-03-12 02:47:58 +00:00
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// Install operations.
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2019-03-13 02:46:31 +00:00
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install_instructions(bus_steps);
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// Realise the exception programs as direct pointers.
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reset_program_ = &all_bus_steps_[reset_offset];
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2019-03-12 02:47:58 +00:00
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2019-03-10 21:27:34 +00:00
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// Set initial state. Largely TODO.
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active_step_ = reset_program_;
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effective_address_ = 0;
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2019-03-10 21:42:13 +00:00
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is_supervisor_ = 1;
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2019-03-09 05:00:23 +00:00
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}
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2019-03-16 21:54:58 +00:00
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size_t ProcessorStorage::assemble_program(const char *access_pattern, const std::vector<uint32_t *> &addresses, bool read_full_words) {
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const size_t start = all_bus_steps_.size();
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2019-03-14 01:08:13 +00:00
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auto address_iterator = addresses.begin();
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RegisterPair32 *scratch_data_read = bus_data_;
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RegisterPair32 *scratch_data_write = bus_data_;
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2019-03-09 05:00:23 +00:00
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// Parse the access pattern to build microcycles.
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while(*access_pattern) {
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BusStep step;
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2019-03-09 05:00:23 +00:00
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switch(*access_pattern) {
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case '\t': case ' ': // White space acts as a no-op; it's for clarity only.
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++access_pattern;
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2019-03-09 05:00:23 +00:00
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break;
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2019-03-10 21:27:34 +00:00
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case 'n': // This might be a plain NOP cycle, in which some internal calculation occurs,
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// or it might pair off with something afterwards.
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switch(access_pattern[1]) {
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default: // This is probably a pure NOP; if what comes after this 'n' isn't actually
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// valid, it should be caught in the outer switch the next time around the loop.
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2019-03-13 02:46:31 +00:00
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all_bus_steps_.push_back(step);
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++access_pattern;
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break;
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case '-': // This is two NOPs in a row.
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all_bus_steps_.push_back(step);
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all_bus_steps_.push_back(step);
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2019-03-10 21:27:34 +00:00
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access_pattern += 2;
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break;
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case 'F': // Fetch SSP MSW.
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case 'f': // Fetch SSP LSW.
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step.microcycle.length = HalfCycles(5);
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2019-03-16 21:54:58 +00:00
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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2019-03-10 21:27:34 +00:00
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step.microcycle.address = &effective_address_;
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step.microcycle.value = isupper(access_pattern[1]) ? &stack_pointers_[1].halves.high : &stack_pointers_[1].halves.low;
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2019-03-13 02:46:31 +00:00
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all_bus_steps_.push_back(step);
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step.microcycle.length = HalfCycles(3);
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2019-03-16 21:54:58 +00:00
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step.microcycle.operation = Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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2019-03-13 02:46:31 +00:00
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step.action = BusStep::Action::IncrementEffectiveAddress;
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all_bus_steps_.push_back(step);
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2019-03-10 21:27:34 +00:00
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access_pattern += 2;
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break;
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case 'V': // Fetch exception vector low.
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case 'v': // Fetch exception vector high.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &effective_address_;
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step.microcycle.value = isupper(access_pattern[1]) ? &program_counter_.halves.high : &program_counter_.halves.low;
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2019-03-13 02:46:31 +00:00
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all_bus_steps_.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = BusStep::Action::IncrementEffectiveAddress;
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all_bus_steps_.push_back(step);
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2019-03-10 21:27:34 +00:00
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access_pattern += 2;
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break;
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case 'p': // Fetch from the program counter into the prefetch queue.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &program_counter_.full;
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step.microcycle.value = &prefetch_queue_[1];
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step.action = BusStep::Action::AdvancePrefetch;
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all_bus_steps_.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = BusStep::Action::IncrementProgramCounter;
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all_bus_steps_.push_back(step);
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2019-03-10 21:27:34 +00:00
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access_pattern += 2;
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break;
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2019-03-14 01:08:13 +00:00
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case 'r': // Fetch LSW (or only) word (/byte)
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case 'R': // Fetch MSW word
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case 'w': // Store LSW (or only) word (/byte)
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case 'W': { // Store MSW word
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const bool is_read = tolower(access_pattern[1]) == 'r';
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RegisterPair32 **scratch_data = is_read ? &scratch_data_read : &scratch_data_write;
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step.microcycle.length = HalfCycles(5);
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2019-03-16 21:54:58 +00:00
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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2019-03-14 01:08:13 +00:00
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(access_pattern[1]) ? &(*scratch_data)->halves.high : &(*scratch_data)->halves.low;
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all_bus_steps_.push_back(step);
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step.microcycle.length = HalfCycles(3);
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2019-03-16 21:54:58 +00:00
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step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
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2019-03-14 01:08:13 +00:00
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all_bus_steps_.push_back(step);
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++address_iterator;
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if(!isupper(access_pattern[1])) ++(*scratch_data);
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access_pattern += 2;
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} break;
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2019-03-10 21:27:34 +00:00
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}
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2019-03-09 05:00:23 +00:00
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break;
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2019-03-10 21:27:34 +00:00
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default:
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std::cerr << "MC68000 program builder; Unknown access type " << *access_pattern << std::endl;
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assert(false);
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2019-03-09 05:00:23 +00:00
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}
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}
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2019-03-10 21:27:34 +00:00
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// Add a final 'ScheduleNextProgram' sentinel.
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2019-03-13 02:46:31 +00:00
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BusStep end_program;
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end_program.action = BusStep::Action::ScheduleNextProgram;
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all_bus_steps_.push_back(end_program);
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2019-03-09 05:00:23 +00:00
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2019-03-13 02:46:31 +00:00
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return start;
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}
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ProcessorStorage::BusStepCollection ProcessorStorage::assemble_standard_bus_steps() {
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ProcessorStorage::BusStepCollection collection;
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collection.four_step_Dn = assemble_program("np");
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collection.six_step_Dn = assemble_program("np n");
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2019-03-14 01:08:13 +00:00
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for(int s = 0; s < 8; ++s) {
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for(int d = 0; d < 8; ++d) {
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2019-03-16 21:54:58 +00:00
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collection.double_predec_byte[s][d] = assemble_program("n nr nr np nw", { &address_[s].full, &address_[d].full, &address_[d].full }, false);
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collection.double_predec_word[s][d] = assemble_program("n nr nr np nw", { &address_[s].full, &address_[d].full, &address_[d].full });
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// collection.double_predec_long[s][d] = assemble_program("n nr nR nr nR nw np nW", { &address_[s].full, &address_[d].full, &address_[d].full });
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}
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}
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2019-03-13 02:46:31 +00:00
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return collection;
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2019-03-09 05:00:23 +00:00
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}
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2019-03-12 02:47:58 +00:00
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/*
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install_instruction acts, in effect, in the manner of a disassembler. So this class is
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formulated to run through all potential 65536 instuction encodings and attempt to
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disassemble each, rather than going in the opposite direction.
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This has two benefits:
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(i) which addressing modes go with which instructions falls out automatically;
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(ii) it is a lot easier during the manual verification stage of development to work
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from known instructions to their disassembly rather than vice versa; especially
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(iii) given that there are plentiful disassemblers against which to test work in progress.
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*/
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2019-03-13 02:46:31 +00:00
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void ProcessorStorage::install_instructions(const BusStepCollection &bus_step_collection) {
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enum class Decoder {
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Decimal,
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RegOpModeReg,
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SizeModeRegisterImmediate,
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DataSizeModeQuick
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2019-03-12 02:47:58 +00:00
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};
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struct PatternMapping {
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uint16_t mask, value;
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Operation operation;
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Decoder decoder;
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};
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/*
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2019-03-13 02:46:31 +00:00
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Inspired partly by 'wrm' (https://github.com/wrm-za I assume); the following
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table draws from the M68000 Programmer's Reference Manual, currently available at
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2019-03-12 02:47:58 +00:00
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https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf
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2019-03-13 02:46:31 +00:00
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After each line is the internal page number on which documentation of that
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instruction mapping can be found, followed by the page number within the PDF
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linked above.
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NB: a vector is used to allow easy iteration.
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*/
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const std::vector<PatternMapping> mappings = {
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{0xf1f0, 0x8100, Operation::SBCD, Decoder::Decimal}, // 4-171 (p275)
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{0xf1f0, 0xc100, Operation::ABCD, Decoder::Decimal}, // 4-3 (p107)
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{0xf000, 0x8000, Operation::OR, Decoder::RegOpModeReg}, // 4-150 (p226)
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{0xf000, 0x9000, Operation::SUB, Decoder::RegOpModeReg}, // 4-174 (p278)
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{0xf000, 0xb000, Operation::EOR, Decoder::RegOpModeReg}, // 4-100 (p204)
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{0xf000, 0xc000, Operation::AND, Decoder::RegOpModeReg}, // 4-15 (p119)
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{0xf000, 0xd000, Operation::ADD, Decoder::RegOpModeReg}, // 4-4 (p108)
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{0xff00, 0x0600, Operation::ADD, Decoder::SizeModeRegisterImmediate}, // 4-9 (p113)
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{0xff00, 0x0600, Operation::ADD, Decoder::DataSizeModeQuick}, // 4-11 (p115)
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};
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2019-03-14 01:08:13 +00:00
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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2019-03-12 02:47:58 +00:00
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// Perform a linear search of the mappings above for this instruction.
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2019-03-14 23:32:15 +00:00
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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2019-03-13 02:46:31 +00:00
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for(const auto &mapping: mappings) {
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if((instruction & mapping.mask) == mapping.value) {
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2019-03-14 01:08:13 +00:00
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// Install the operation and make a note of where micro-ops begin.
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instructions[instruction].operation = mapping.operation;
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micro_op_pointers[instruction] = all_micro_ops_.size();
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2019-03-13 02:46:31 +00:00
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switch(mapping.decoder) {
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case Decoder::Decimal: {
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2019-03-14 23:32:15 +00:00
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const int destination = (instruction >> 9) & 7;
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2019-03-13 02:46:31 +00:00
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const int source = instruction & 7;
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2019-03-14 01:08:13 +00:00
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2019-03-13 02:46:31 +00:00
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if(instruction & 8) {
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2019-03-14 01:08:13 +00:00
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instructions[instruction].source = &bus_data_[0];
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instructions[instruction].destination = &bus_data_[1];
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2019-03-15 01:22:02 +00:00
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all_micro_ops_.emplace_back(
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MicroOp::Action::PredecrementSourceAndDestination1,
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&all_bus_steps_[bus_step_collection.double_predec_byte[source][destination]]);
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all_micro_ops_.emplace_back(MicroOp::Action::PerformOperation);
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2019-03-14 01:08:13 +00:00
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all_micro_ops_.emplace_back();
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2019-03-13 02:46:31 +00:00
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} else {
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instructions[instruction].source = &data_[source];
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instructions[instruction].destination = &data_[destination];
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2019-03-14 01:08:13 +00:00
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2019-03-15 01:22:02 +00:00
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all_micro_ops_.emplace_back(
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MicroOp::Action::PerformOperation,
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&all_bus_steps_[bus_step_collection.six_step_Dn]);
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2019-03-14 01:08:13 +00:00
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all_micro_ops_.emplace_back();
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2019-03-13 02:46:31 +00:00
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}
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} break;
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case Decoder::RegOpModeReg: {
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} break;
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default:
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std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
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break;
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}
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2019-03-14 01:08:13 +00:00
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// Don't search further through the list of possibilities.
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2019-03-13 02:46:31 +00:00
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break;
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2019-03-12 02:47:58 +00:00
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}
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}
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}
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2019-03-14 01:08:13 +00:00
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// Finalise micro-op pointers.
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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if(micro_op_pointers[instruction] != std::numeric_limits<size_t>::max()) {
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instructions[instruction].micro_operations = &all_micro_ops_[micro_op_pointers[instruction]];
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}
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}
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2019-03-12 02:47:58 +00:00
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}
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