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CLK/Processors/68000/Implementation/68000Storage.cpp

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Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
//
// 68000Storage.cpp
// Clock Signal
//
// Created by Thomas Harte on 08/03/2019.
// Copyright © 2019 Thomas Harte. All rights reserved.
//
#include "../68000.hpp"
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
#include <algorithm>
Introduces a couple of missing #includes.
2019-05-03 18:37:05 +00:00
#include <cassert>
Adds further missing includes.
2019-05-03 18:42:36 +00:00
#include <ctime>
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
#include <map>
Also previously missing: vector.h.
2019-05-03 18:43:31 +00:00
#include <vector>
Introduces a couple of missing #includes.
2019-05-03 18:37:05 +00:00
#include <sstream>
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-13 02:46:31 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
namespace CPU {
namespace MC68000 {
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
#define Dn 0x00
#define An 0x01
#define Ind 0x02
#define PostInc 0x03
#define PreDec 0x04
#define d16An 0x05
#define d8AnXn 0x06
#define XXXw 0x10
#define XXXl 0x11
#define d16PC 0x12
#define d8PCXn 0x13
#define Imm 0x14
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
struct ProcessorStorageConstructor {
ProcessorStorageConstructor(ProcessorStorage &storage) : storage_(storage) {}
using BusStep = ProcessorStorage::BusStep;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
/*!
*/
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
int calc_action_for_mode(int mode) const {
using Action = ProcessorBase::MicroOp::Action;
switch(mode & 0xff) {
Fixes a bunch of (d16, An)-type MOVEs and implements MOVE (XXX).wl, (d16,An)/etc.
2019-04-17 20:13:35 +00:00
default: assert(false);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case d16PC: return int(Action::CalcD16PC);
case d8PCXn: return int(Action::CalcD8PCXn);
case d16An: return int(Action::CalcD16An);
case d8AnXn: return int(Action::CalcD8AnXn);
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
}
}
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
int address_assemble_for_mode(int mode) const {
using Action = ProcessorBase::MicroOp::Action;
assert((mode & 0xff) == XXXw || (mode & 0xff) == XXXl);
return int(((mode & 0xff) == XXXw) ? Action::AssembleWordAddressFromPrefetch : Action::AssembleLongWordAddressFromPrefetch);
}
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
int address_action_for_mode(int mode) const {
using Action = ProcessorBase::MicroOp::Action;
switch(mode & 0xff) {
default: assert(false);
case d16PC: return int(Action::CalcD16PC);
case d8PCXn: return int(Action::CalcD8PCXn);
case d16An: return int(Action::CalcD16An);
case d8AnXn: return int(Action::CalcD8AnXn);
case XXXw: return int(Action::AssembleWordAddressFromPrefetch);
case XXXl: return int(Action::AssembleLongWordAddressFromPrefetch);
}
}
int combined_mode(int mode, int reg, bool collapse_an_dn = false, bool collapse_postinc = false) {
if(collapse_an_dn && mode == An) mode = Dn;
if(collapse_postinc && mode == PostInc) mode = Ind;
return (mode == 7) ? (0x10 | reg) : mode;
}
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
int data_assemble_for_mode(int mode) const {
using Action = ProcessorBase::MicroOp::Action;
assert((mode & 0xff) == XXXw || (mode & 0xff) == XXXl);
return int(((mode & 0xff) == XXXw) ? Action::AssembleWordDataFromPrefetch : Action::AssembleLongWordDataFromPrefetch);
}
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
int byte_inc(int reg) const {
using Action = ProcessorBase::MicroOp::Action;
// Special case: stack pointer byte accesses adjust by two.
return int((reg == 7) ? Action::Increment2 : Action::Increment1);
}
int byte_dec(int reg) const {
using Action = ProcessorBase::MicroOp::Action;
// Special case: stack pointer byte accesses adjust by two.
return int((reg == 7) ? Action::Decrement2 : Action::Decrement1);
}
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
int increment_action(bool is_long_word_access, bool is_byte_access, int reg) const {
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
using Action = ProcessorBase::MicroOp::Action;
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
if(is_long_word_access) return int(Action::Increment4);
if(is_byte_access) return byte_inc(reg);
return int(Action::Increment2);
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
}
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
int decrement_action(bool is_long_word_access, bool is_byte_access, int reg) const {
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
using Action = ProcessorBase::MicroOp::Action;
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
if(is_long_word_access) return int(Action::Decrement4);
if(is_byte_access) return byte_dec(reg);
return int(Action::Decrement2);
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
}
Adds missing addressing modes for ADDA and SUBA. ... reducing missing opcodes to 1941.
2019-04-27 21:22:26 +00:00
#define pseq(x, m) ((((m)&0xff) == d8AnXn) || (((m)&0xff) == d8PCXn) ? "n " x : x)
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
/*!
Installs BusSteps that implement the described program into the relevant
instance storage, returning the offset within @c all_bus_steps_ at which
the generated steps begin.
@param access_pattern A string describing the bus activity that occurs
during this program. This should follow the same general pattern as
those in yacht.txt; full description below.
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
@param addresses A vector of the addresses to place on the bus coincident
with those acess steps that require them.
@param read_full_words @c true to indicate that read and write operations are
selecting a full word; @c false to signal byte accesses only.
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
@discussion
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
The access pattern is defined to correlate closely to that in yacht.txt; it is
a space-separated sequence of the following actions:
* n: no operation for four cycles; data bus is not used;
* nn: no operation for eight cycles; data bus is not used;
Implements ASL, ASR, LSL and LSR.
2019-04-11 02:31:04 +00:00
* r: a 'replaceable'-length no operation; data bus is not used and no guarantees are
made about the length of the cycle other than that when it reaches the interpreter,
it is safe to alter the length and leave it altered;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
* np: program fetch; reads from the PC and adds two to it, advancing the prefetch queue;
* nW: write MSW of something onto the bus;
* nw: write LSW of something onto the bus;
* nR: read MSW of something from the bus into the source latch;
* nr: read LSW of soemthing from the bus into the source latch;
* nRd: read MSW of something from the bus into the destination latch;
* nrd: read LSW of soemthing from the bus into the destination latch;
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
* nS: push the MSW of something onto the stack **and then** decrement the pointer;
* ns: push the LSW of something onto the stack **and then** decrement the pointer;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
* nU: pop the MSW of something from the stack;
* nu: pop the LSW of something from the stack;
* nV: fetch a vector's MSW;
* nv: fetch a vector's LSW;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
* i: acquire interrupt vector in an IACK cycle;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
* nF: fetch the SSPs MSW;
* nf: fetch the SSP's LSW;
* _: hold the reset line active for the usual period.
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
* tas: perform the final 6 cycles of a TAS: like an n nw but with the address strobe active for the entire period.
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
* int: the interrupt acknowledge cycle.
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Quite a lot of that is duplicative, implying both something about internal
state and something about what's observable on the bus, but it's helpful to
stick to that document's coding exactly for easier debugging.
Effective address adjustments now have to be explicit.
2019-04-03 23:13:10 +00:00
np fetches will fill the prefetch queue, attaching an action to both the
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
step that precedes them and to themselves. The SSP fetches will go straight
to the SSP.
Other actions will by default act via effective_address_ and bus_data_.
The user should fill in the steps necessary to get data into or extract
data from those.
Effective address adjustments now have to be explicit.
2019-04-03 23:13:10 +00:00
nr/nw-type operations may have a + or - suffix; if such a suffix is attached
then the corresponding effective address will be incremented or decremented
by two after the cycle has completed.
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
*/
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
size_t assemble_program(std::string access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
auto address_iterator = addresses.begin();
using Action = BusStep::Action;
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
std::vector<BusStep> steps;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
std::stringstream stream(access_pattern);
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
// Tokenise the access pattern by splitting on spaces.
std::string token;
while(stream >> token) {
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
ProcessorBase::BusStep step;
Effective address adjustments now have to be explicit.
2019-04-03 23:13:10 +00:00
// Check for a plus-or-minus suffix.
int post_adjustment = 0;
if(token.back() == '-' || token.back() == '+') {
if(token.back() == '-') {
post_adjustment = -1;
}
if(token.back() == '+') {
post_adjustment = 1;
}
token.pop_back();
}
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
// Do nothing (possibly twice).
if(token == "n" || token == "nn") {
if(token.size() == 2) {
Implements ASL, ASR, LSL and LSR.
2019-04-11 02:31:04 +00:00
step.microcycle.length = HalfCycles(8);
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
}
Implements ASL, ASR, LSL and LSR.
2019-04-11 02:31:04 +00:00
steps.push_back(step);
continue;
}
// Do nothing, but with a length that definitely won't map it to the other do-nothings.
if(token == "r"){
step.microcycle.length = HalfCycles(0);
steps.push_back(step);
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
continue;
}
// Fetch SSP.
if(token == "nF" || token == "nf") {
step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
step.microcycle.address = &storage_.effective_address_[0].full;
step.microcycle.value = isupper(token[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
steps.push_back(step);
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
step.action = Action::IncrementEffectiveAddress0;
steps.push_back(step);
continue;
}
// Fetch exception vector.
if(token == "nV" || token == "nv") {
step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
step.microcycle.address = &storage_.effective_address_[0].full;
step.microcycle.value = isupper(token[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
steps.push_back(step);
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
step.action = Action::IncrementEffectiveAddress0;
steps.push_back(step);
continue;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
// Fetch from the program counter into the prefetch queue.
if(token == "np") {
step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
step.microcycle.address = &storage_.program_counter_.full;
step.microcycle.value = &storage_.prefetch_queue_.halves.low;
step.action = Action::AdvancePrefetch;
steps.push_back(step);
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
step.action = Action::IncrementProgramCounter;
steps.push_back(step);
continue;
}
// The reset cycle.
if(token == "_") {
step.microcycle.length = HalfCycles(248);
step.microcycle.operation = Microcycle::Reset;
steps.push_back(step);
continue;
}
// A standard read or write.
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
if(token == "nR" || token == "nr" || token == "nW" || token == "nw" || token == "nRd" || token == "nrd" || token == "nWr" || token == "nwr") {
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
const bool is_read = tolower(token[1]) == 'r';
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
const bool use_source_storage = (token == "nR" || token == "nr" || token == "nWr" || token == "nwr");
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
RegisterPair32 *const scratch_data = use_source_storage ? &storage_.source_bus_data_[0] : &storage_.destination_bus_data_[0];
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
assert(address_iterator != addresses.end());
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
step.microcycle.address = *address_iterator;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
steps.push_back(step);
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | (is_read ? Microcycle::Read : 0) | (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte);
Effective address adjustments now have to be explicit.
2019-04-03 23:13:10 +00:00
if(post_adjustment) {
Corrects addressing behaviour of nRd[+-].
2019-04-17 12:53:34 +00:00
// nr and nR should affect address 0; nw, nW, nrd and nRd should affect address 1.
if(tolower(token[1]) == 'r' && token.size() == 2) {
Effective address adjustments now have to be explicit.
2019-04-03 23:13:10 +00:00
step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress0 : Action::DecrementEffectiveAddress0;
} else {
step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress1 : Action::DecrementEffectiveAddress1;
}
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
}
steps.push_back(step);
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
++address_iterator;
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
continue;
}
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
// The completing part of a TAS.
if(token == "tas") {
RegisterPair32 *const scratch_data = &storage_.destination_bus_data_[0];
assert(address_iterator != addresses.end());
step.microcycle.length = HalfCycles(9);
step.microcycle.operation = Microcycle::SameAddress;
step.microcycle.address = *address_iterator;
step.microcycle.value = &scratch_data->halves.low;
steps.push_back(step);
step.microcycle.length = HalfCycles(3);
step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectByte;
steps.push_back(step);
++address_iterator;
continue;
}
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
// A stack write.
if(token == "nS" || token == "ns") {
step.microcycle.operation = Microcycle::NewAddress;
step.microcycle.address = &storage_.effective_address_[1].full;
Implements LINK and UNLINK. Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against. Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 21:12:31 +00:00
step.microcycle.value = isupper(token[1]) ? &storage_.destination_bus_data_[0].halves.high : &storage_.destination_bus_data_[0].halves.low;
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
steps.push_back(step);
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectWord;
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
step.action = Action::DecrementEffectiveAddress1;
steps.push_back(step);
continue;
}
// A stack read.
if(token == "nU" || token == "nu") {
RegisterPair32 *const scratch_data = &storage_.source_bus_data_[0];
step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read;
step.microcycle.address = &storage_.effective_address_[0].full;
step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
steps.push_back(step);
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::SelectWord;
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
step.action = Action::IncrementEffectiveAddress0;
steps.push_back(step);
continue;
}
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
// Interrupt acknowledge.
if(token == "int") {
Corrects internet response to work as currently implemented. Also makes corrections to the bus error and address error exceptions.
2019-05-02 01:59:06 +00:00
step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::NewAddress;
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
step.microcycle.address = &storage_.effective_address_[0].full; // The selected interrupt should be in bits 1–3; but 0 should be set.
step.microcycle.value = &storage_.source_bus_data_[0].halves.low;
steps.push_back(step);
Corrects internet response to work as currently implemented. Also makes corrections to the bus error and address error exceptions.
2019-05-02 01:59:06 +00:00
step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::SameAddress | Microcycle::SelectByte;
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
steps.push_back(step);
continue;
}
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-31 03:11:39 +00:00
std::cerr << "MC68000 program builder; Unknown access token " << token << std::endl;
assert(false);
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-12 02:47:58 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
// Add a final 'ScheduleNextProgram' sentinel.
BusStep end_program;
end_program.action = Action::ScheduleNextProgram;
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
steps.push_back(end_program);
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
// If the new steps already exist, just return the existing index to them;
// otherwise insert them.
const auto position = std::search(storage_.all_bus_steps_.begin(), storage_.all_bus_steps_.end(), steps.begin(), steps.end());
if(position != storage_.all_bus_steps_.end()) {
return size_t(position - storage_.all_bus_steps_.begin());
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
Restores accidentally-cropped functionality.
2019-04-30 02:10:00 +00:00
const auto start = storage_.all_bus_steps_.size();
std::copy(steps.begin(), steps.end(), std::back_inserter(storage_.all_bus_steps_));
return start;
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
/*
// If the new steps already exist, just return the existing index to them;
// otherwise insert them. A lookup table of steps to start positions within
// all_bus_steps_ is maintained to shorten setup time here
auto potential_locations = locations_by_bus_step_[steps.front()];
for(auto index: potential_locations) {
if(index + steps.size() >= storage_.all_bus_steps_.size()) continue;
if(std::equal(
storage_.all_bus_steps_.begin() + ssize_t(index),
storage_.all_bus_steps_.begin() + ssize_t(index + steps.size()),
steps.begin())) {
return index;
}
}
// Copy to the end, and update potential_locations.
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
const auto start = storage_.all_bus_steps_.size();
std::copy(steps.begin(), steps.end(), std::back_inserter(storage_.all_bus_steps_));
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
auto index = start;
for(const auto &step: steps) {
locations_by_bus_step_[step].push_back(index);
++index;
}
Restores accidentally-cropped functionality.
2019-04-30 02:10:00 +00:00
return start;*/
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
/*!
Walks through the sequence of bus steps beginning at @c start, replacing the value supplied for each write
encountered with the respective value from @c values.
*/
Reduces conversions to vector.
2019-05-30 16:08:35 +00:00
void replace_write_values(BusStep *start, const std::initializer_list<RegisterPair16 *> &values) {
Ensures `replace_write_values` works in release builds.
2019-05-29 23:00:53 +00:00
const auto end = replace_write_values(start, values.begin());
assert(end == values.end());
Eliminates further type conversion warnings.
2019-06-13 14:20:17 +00:00
(void)end;
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
}
/*!
Walks through the sequence of micro-ops beginning at @c start, replacing the value supplied for each write
encountered in each micro-op's bus steps with the respective value from @c values.
*/
Reduces conversions to vector.
2019-05-30 16:08:35 +00:00
void replace_write_values(ProcessorBase::MicroOp *start, const std::initializer_list<RegisterPair16 *> &values) {
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
auto value = values.begin();
while(!start->is_terminal()) {
value = replace_write_values(start->bus_program, value);
++start;
}
assert(value == values.end());
}
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
/*!
Disassembles the instruction @c instruction and inserts it into the
appropriate lookup tables.
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
install_instruction acts, in effect, in the manner of a disassembler. So this class is
formulated to run through all potential 65536 instuction encodings and attempt to
disassemble each, rather than going in the opposite direction.
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
This has two benefits:
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
(i) which addressing modes go with which instructions falls out automatically;
(ii) it is a lot easier during the manual verification stage of development to work
from known instructions to their disassembly rather than vice versa; especially
(iii) given that there are plentiful disassemblers against which to test work in progress.
*/
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
void install_instructions() {
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
enum class Decoder {
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
ABCD_SBCD, // Maps source and desintation registers and a register/memory selection bit to an ABCD or SBCD.
ADD_SUB, // Maps a register and a register and mode to an ADD or SUB.
ADDA_SUBA, // Maps a destination register and a source mode and register to an ADDA or SUBA.
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
ADDQ_SUBQ, // Maps a register and a mode to an ADDQ or SUBQ.
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
ADDX_SUBX, // Maps source and destination registers, and register/memory mode to an ADDX or SUBX.
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
AND_OR_EOR, // Maps a source register, operation mode and destination register and mode to an AND, OR or EOR.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
BRA, // Maps to a BRA. All fields are decoded at runtime.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
Bcc_BSR, // Maps to a Bcc or BSR. Other than determining the type of operation, fields are decoded at runtime.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
BTST, // Maps a source register and a destination register and mode to a BTST.
BTSTIMM, // Maps a destination mode and register to a BTST #.
Implements BCLR.
2019-04-15 22:11:02 +00:00
BCLR, // Maps a source register and a destination register and mode to a BCLR.
BCLRIMM, // Maps a destination mode and register to a BCLR #.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
CLR_NEG_NEGX_NOT, // Maps a destination mode and register to a CLR, NEG, NEGX or NOT.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
CMP, // Maps a destination register and a source mode and register to a CMP.
CMPI, // Maps a destination mode and register to a CMPI.
CMPA, // Maps a destination register and a source mode and register to a CMPA.
CMPM, // Maps to a CMPM.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
EORI_ORI_ANDI_SUBI_ADDI, // Maps a mode and register to one of EORI, ORI, ANDI, SUBI or ADDI.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
JMP, // Maps a mode and register to a JMP.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
JSR, // Maps a mode and register to a JSR.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
LEA, // Maps a destination register and a source mode and register to an LEA.
MOVE, // Maps a source mode and register and a destination mode and register to a MOVE.
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
MOVEtoSRCCR, // Maps a source mode and register to a MOVE to SR or MOVE to CCR.
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
MOVEfromSR_NBCD, // Maps a source mode and register to a MOVE fom SR.
Cleans up commenting.
2019-04-09 02:51:18 +00:00
MOVEq, // Maps a destination register to a MOVEQ.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
MULU_MULS, // Maps a destination register and a source mode and register to a MULU or MULS.
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
DIVU_DIVS, // Maps a destination register and a source mode and register to a DIVU or DIVS.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
Cleans up commenting.
2019-04-09 02:51:18 +00:00
RESET, // Maps to a RESET.
Stepping gingerly onwards, adds a double-decoding test. As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
2019-04-09 20:54:41 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
ASLR_LSLR_ROLR_ROXLRr, // Maps a destination register to a AS[L/R], LS[L/R], RO[L/R], ROX[L/R]; shift quantities are
Stepping gingerly onwards, adds a double-decoding test. As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
2019-04-09 20:54:41 +00:00
// decoded at runtime.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
ASLR_LSLR_ROLR_ROXLRm, // Maps a destination mode and register to a memory-based AS[L/R], LS[L/R], RO[L/R], ROX[L/R].
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
MOVEM, // Maps a mode and register as if they were a 'destination' and sets up bus steps with a suitable
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
// hole for the runtime part to install proper MOVEM activity.
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
MOVEP, // Maps a data register, address register and operation mode to a MOVEP.
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
Makes an attempt at RTE and RTR.
2019-04-19 00:50:58 +00:00
RTE_RTR, // Maps to an RTE/RTR.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
Scc_DBcc, // Maps a mode and destination register to either a DBcc or Scc.
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
TST, // Maps a mode and register to a TST.
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
RTS, // Maps to an RST.
Implements MOVE to/from USP.
2019-04-17 20:58:59 +00:00
MOVEUSP, // Maps a direction and register to a MOVE [to/from] USP.
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
TRAP, // Maps to a TRAP.
Takes a run at TRAPV. ... to leave 1466 as the unimplemented count.
2019-04-28 19:52:58 +00:00
TRAPV, // Maps to a TRAPV.
Attempts an implementation of CHK. 1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 19:47:21 +00:00
CHK, // Maps to a CHK.
Adds the official NOP. Which is a freebie.
2019-04-19 03:46:01 +00:00
NOP, // Maps to a NOP.
Implements EXG and SWAP.
2019-04-19 15:27:43 +00:00
EXG, // Maps source and destination registers and an operation mode to an EXG.
Implements EXT.
2019-04-25 22:22:19 +00:00
EXT_SWAP, // Maps a source register to a SWAP or EXT.
Implements ANDI/ORI/EOR to SR/CCR.
2019-04-24 21:38:59 +00:00
EORI_ORI_ANDI_SR, // Maps to an EORI, ORI or ANDI to SR/CCR.
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
BCHG_BSET, // Maps a mode and register, and possibly a source register, to a BCHG or BSET.
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
TAS, // Maps a mode and register to a TAS.
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
PEA, // Maps a mode and register to a PEA.
Implements LINK and UNLINK. Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against. Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 21:12:31 +00:00
LINK, // Maps a register to a LINK.
UNLINK, // Maps a register to an UNLINK.
It leads to a TODO, but implemented decoding and initial setup of STOPpages.
2019-04-29 23:30:00 +00:00
STOP, // Maps to a STOP.
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
};
using Operation = ProcessorStorage::Operation;
using Action = ProcessorStorage::MicroOp::Action;
Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes. With only MOVEs from those to a data register implemented so far.
2019-03-19 02:51:32 +00:00
using MicroOp = ProcessorBase::MicroOp;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
struct PatternMapping {
uint16_t mask, value;
Operation operation;
Decoder decoder;
};
/*
Inspired partly by 'wrm' (https://github.com/wrm-za I assume); the following
table draws from the M68000 Programmer's Reference Manual, currently available at
https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf
After each line is the internal page number on which documentation of that
instruction mapping can be found, followed by the page number within the PDF
linked above.
NB: a vector is used to allow easy iteration.
*/
Reduces conversions to vector.
2019-05-30 16:08:35 +00:00
const std::initializer_list<PatternMapping> mappings = {
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
{0xf1f0, 0xc100, Operation::ABCD, Decoder::ABCD_SBCD}, // 4-3 (p107)
{0xf1f0, 0x8100, Operation::SBCD, Decoder::ABCD_SBCD}, // 4-171 (p275)
{0xffc0, 0x4800, Operation::NBCD, Decoder::MOVEfromSR_NBCD}, // 4-142 (p246)
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
{0xf0c0, 0xc000, Operation::ANDb, Decoder::AND_OR_EOR}, // 4-15 (p119)
{0xf0c0, 0xc040, Operation::ANDw, Decoder::AND_OR_EOR}, // 4-15 (p119)
{0xf0c0, 0xc080, Operation::ANDl, Decoder::AND_OR_EOR}, // 4-15 (p119)
{0xf0c0, 0x8000, Operation::ORb, Decoder::AND_OR_EOR}, // 4-150 (p254)
{0xf0c0, 0x8040, Operation::ORw, Decoder::AND_OR_EOR}, // 4-150 (p254)
{0xf0c0, 0x8080, Operation::ORl, Decoder::AND_OR_EOR}, // 4-150 (p254)
{0xf0c0, 0xb000, Operation::EORb, Decoder::AND_OR_EOR}, // 4-100 (p204)
{0xf0c0, 0xb040, Operation::EORw, Decoder::AND_OR_EOR}, // 4-100 (p204)
{0xf0c0, 0xb080, Operation::EORl, Decoder::AND_OR_EOR}, // 4-100 (p204)
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xffc0, 0x0600, Operation::ADDb, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-9 (p113)
{0xffc0, 0x0640, Operation::ADDw, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-9 (p113)
{0xffc0, 0x0680, Operation::ADDl, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-9 (p113)
Fixes crossed-over decoding of EORI and ORI.
2019-04-29 21:45:52 +00:00
{0xffc0, 0x0200, Operation::ANDb, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-18 (p122)
{0xffc0, 0x0240, Operation::ANDw, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-18 (p122)
{0xffc0, 0x0280, Operation::ANDl, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-18 (p122)
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
Fixes crossed-over decoding of EORI and ORI.
2019-04-29 21:45:52 +00:00
{0xffc0, 0x0000, Operation::ORb, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-153 (p257)
{0xffc0, 0x0040, Operation::ORw, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-153 (p257)
{0xffc0, 0x0080, Operation::ORl, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-153 (p257)
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
Fixes crossed-over decoding of EORI and ORI.
2019-04-29 21:45:52 +00:00
{0xffc0, 0x0a00, Operation::EORb, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-102 (p206)
{0xffc0, 0x0a40, Operation::EORw, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-102 (p206)
{0xffc0, 0x0a80, Operation::EORl, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-102 (p206)
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xffc0, 0x0400, Operation::SUBb, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-179 (p283)
{0xffc0, 0x0440, Operation::SUBw, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-179 (p283)
{0xffc0, 0x0480, Operation::SUBl, Decoder::EORI_ORI_ANDI_SUBI_ADDI}, // 4-179 (p283)
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
{0xf000, 0x1000, Operation::MOVEb, Decoder::MOVE}, // 4-116 (p220)
{0xf000, 0x2000, Operation::MOVEl, Decoder::MOVE}, // 4-116 (p220)
{0xf000, 0x3000, Operation::MOVEw, Decoder::MOVE}, // 4-116 (p220)
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
{0xffc0, 0x46c0, Operation::MOVEtoSR, Decoder::MOVEtoSRCCR}, // 6-19 (p473)
{0xffc0, 0x44c0, Operation::MOVEtoCCR, Decoder::MOVEtoSRCCR}, // 4-123 (p227)
{0xffc0, 0x40c0, Operation::MOVEfromSR, Decoder::MOVEfromSR_NBCD}, // 6-17 (p471)
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
{0xf1c0, 0xb000, Operation::CMPb, Decoder::CMP}, // 4-75 (p179)
{0xf1c0, 0xb040, Operation::CMPw, Decoder::CMP}, // 4-75 (p179)
{0xf1c0, 0xb080, Operation::CMPl, Decoder::CMP}, // 4-75 (p179)
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
{0xf1c0, 0xb0c0, Operation::CMPw, Decoder::CMPA}, // 4-77 (p181)
{0xf1c0, 0xb1c0, Operation::CMPl, Decoder::CMPA}, // 4-77 (p181)
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
{0xffc0, 0x0c00, Operation::CMPb, Decoder::CMPI}, // 4-79 (p183)
{0xffc0, 0x0c40, Operation::CMPw, Decoder::CMPI}, // 4-79 (p183)
{0xffc0, 0x0c80, Operation::CMPl, Decoder::CMPI}, // 4-79 (p183)
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
{0xf1f8, 0xb108, Operation::CMPb, Decoder::CMPM}, // 4-81 (p185)
{0xf1f8, 0xb148, Operation::CMPw, Decoder::CMPM}, // 4-81 (p185)
{0xf1f8, 0xb188, Operation::CMPl, Decoder::CMPM}, // 4-81 (p185)
Stepping gingerly onwards, adds a double-decoding test. As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
2019-04-09 20:54:41 +00:00
// {0xff00, 0x6000, Operation::BRA, Decoder::BRA}, // 4-55 (p159) TODO: confirm that this really, really is just a special case of Bcc.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf000, 0x6000, Operation::Bcc, Decoder::Bcc_BSR}, // 4-25 (p129) and 4-59 (p163)
Stepping gingerly onwards, adds a double-decoding test. As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
2019-04-09 20:54:41 +00:00
Implements LEA.
2019-03-27 02:07:28 +00:00
{0xf1c0, 0x41c0, Operation::MOVEAl, Decoder::LEA}, // 4-110 (p214)
Further fixes PEA, and OR/AND/EOR Dn, (An).
2019-05-29 18:37:15 +00:00
{0xffc0, 0x4840, Operation::PEA, Decoder::PEA}, // 4-159 (p263)
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
{0xf100, 0x7000, Operation::MOVEq, Decoder::MOVEq}, // 4-134 (p238)
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
{0xffff, 0x4e70, Operation::None, Decoder::RESET}, // 6-83 (p537)
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
{0xffc0, 0x4ec0, Operation::JMP, Decoder::JMP}, // 4-108 (p212)
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
{0xffc0, 0x4e80, Operation::JMP, Decoder::JSR}, // 4-109 (p213)
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
{0xffff, 0x4e75, Operation::RTS, Decoder::RTS}, // 4-169 (p273)
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf0c0, 0x9000, Operation::SUBb, Decoder::ADD_SUB}, // 4-174 (p278)
{0xf0c0, 0x9040, Operation::SUBw, Decoder::ADD_SUB}, // 4-174 (p278)
{0xf0c0, 0x9080, Operation::SUBl, Decoder::ADD_SUB}, // 4-174 (p278)
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf0c0, 0xd000, Operation::ADDb, Decoder::ADD_SUB}, // 4-4 (p108)
{0xf0c0, 0xd040, Operation::ADDw, Decoder::ADD_SUB}, // 4-4 (p108)
{0xf0c0, 0xd080, Operation::ADDl, Decoder::ADD_SUB}, // 4-4 (p108)
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf1c0, 0xd0c0, Operation::ADDAw, Decoder::ADDA_SUBA}, // 4-7 (p111)
{0xf1c0, 0xd1c0, Operation::ADDAl, Decoder::ADDA_SUBA}, // 4-7 (p111)
{0xf1c0, 0x90c0, Operation::SUBAw, Decoder::ADDA_SUBA}, // 4-177 (p281)
{0xf1c0, 0x91c0, Operation::SUBAl, Decoder::ADDA_SUBA}, // 4-177 (p281)
Adds BTST.
2019-04-05 01:43:22 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf1c0, 0x5000, Operation::ADDQb, Decoder::ADDQ_SUBQ}, // 4-11 (p115)
{0xf1c0, 0x5040, Operation::ADDQw, Decoder::ADDQ_SUBQ}, // 4-11 (p115)
{0xf1c0, 0x5080, Operation::ADDQl, Decoder::ADDQ_SUBQ}, // 4-11 (p115)
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf1c0, 0x5100, Operation::SUBQb, Decoder::ADDQ_SUBQ}, // 4-181 (p285)
{0xf1c0, 0x5140, Operation::SUBQw, Decoder::ADDQ_SUBQ}, // 4-181 (p285)
{0xf1c0, 0x5180, Operation::SUBQl, Decoder::ADDQ_SUBQ}, // 4-181 (p285)
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
{0xf1f0, 0xd100, Operation::ADDXb, Decoder::ADDX_SUBX}, // 4-14 (p118)
{0xf1f0, 0xd140, Operation::ADDXw, Decoder::ADDX_SUBX}, // 4-14 (p118)
{0xf1f0, 0xd180, Operation::ADDXl, Decoder::ADDX_SUBX}, // 4-14 (p118)
{0xf1f0, 0x9100, Operation::SUBXb, Decoder::ADDX_SUBX}, // 4-184 (p288)
{0xf1f0, 0x9140, Operation::SUBXw, Decoder::ADDX_SUBX}, // 4-184 (p288)
{0xf1f0, 0x9180, Operation::SUBXl, Decoder::ADDX_SUBX}, // 4-184 (p288)
Adds BTST.
2019-04-05 01:43:22 +00:00
{0xf1c0, 0x0100, Operation::BTSTb, Decoder::BTST}, // 4-62 (p166)
{0xffc0, 0x0800, Operation::BTSTb, Decoder::BTSTIMM}, // 4-63 (p167)
Implements DBcc.
2019-04-07 03:21:01 +00:00
Implements BCLR.
2019-04-15 22:11:02 +00:00
{0xf1c0, 0x0180, Operation::BCLRb, Decoder::BCLR}, // 4-31 (p135)
{0xffc0, 0x0880, Operation::BCLRb, Decoder::BCLRIMM}, // 4-32 (p136)
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
{0xf0c0, 0x50c0, Operation::Scc, Decoder::Scc_DBcc}, // Scc: 4-173 (p276); DBcc: 4-91 (p195)
{0xffc0, 0x4200, Operation::CLRb, Decoder::CLR_NEG_NEGX_NOT}, // 4-73 (p177)
{0xffc0, 0x4240, Operation::CLRw, Decoder::CLR_NEG_NEGX_NOT}, // 4-73 (p177)
{0xffc0, 0x4280, Operation::CLRl, Decoder::CLR_NEG_NEGX_NOT}, // 4-73 (p177)
{0xffc0, 0x4400, Operation::NEGb, Decoder::CLR_NEG_NEGX_NOT}, // 4-144 (p248)
{0xffc0, 0x4440, Operation::NEGw, Decoder::CLR_NEG_NEGX_NOT}, // 4-144 (p248)
{0xffc0, 0x4480, Operation::NEGl, Decoder::CLR_NEG_NEGX_NOT}, // 4-144 (p248)
{0xffc0, 0x4000, Operation::NEGXb, Decoder::CLR_NEG_NEGX_NOT}, // 4-146 (p250)
{0xffc0, 0x4040, Operation::NEGXw, Decoder::CLR_NEG_NEGX_NOT}, // 4-146 (p250)
{0xffc0, 0x4080, Operation::NEGXl, Decoder::CLR_NEG_NEGX_NOT}, // 4-146 (p250)
{0xffc0, 0x4600, Operation::NOTb, Decoder::CLR_NEG_NEGX_NOT}, // 4-148 (p250)
{0xffc0, 0x4640, Operation::NOTw, Decoder::CLR_NEG_NEGX_NOT}, // 4-148 (p250)
{0xffc0, 0x4680, Operation::NOTl, Decoder::CLR_NEG_NEGX_NOT}, // 4-148 (p250)
{0xf1d8, 0xe100, Operation::ASLb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xf1d8, 0xe140, Operation::ASLw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xf1d8, 0xe180, Operation::ASLl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xffc0, 0xe1c0, Operation::ASLm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-22 (p126)
{0xf1d8, 0xe000, Operation::ASRb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xf1d8, 0xe040, Operation::ASRw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xf1d8, 0xe080, Operation::ASRl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-22 (p126)
{0xffc0, 0xe0c0, Operation::ASRm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-22 (p126)
{0xf1d8, 0xe108, Operation::LSLb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xf1d8, 0xe148, Operation::LSLw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xf1d8, 0xe188, Operation::LSLl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xffc0, 0xe3c0, Operation::LSLm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-113 (p217)
{0xf1d8, 0xe008, Operation::LSRb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xf1d8, 0xe048, Operation::LSRw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xf1d8, 0xe088, Operation::LSRl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-113 (p217)
{0xffc0, 0xe2c0, Operation::LSRm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-113 (p217)
{0xf1d8, 0xe118, Operation::ROLb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xf1d8, 0xe158, Operation::ROLw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xf1d8, 0xe198, Operation::ROLl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xffc0, 0xe7c0, Operation::ROLm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-160 (p264)
{0xf1d8, 0xe018, Operation::RORb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xf1d8, 0xe058, Operation::RORw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xf1d8, 0xe098, Operation::RORl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-160 (p264)
{0xffc0, 0xe6c0, Operation::RORm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-160 (p264)
{0xf1d8, 0xe110, Operation::ROXLb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xf1d8, 0xe150, Operation::ROXLw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xf1d8, 0xe190, Operation::ROXLl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xffc0, 0xe5c0, Operation::ROXLm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-163 (p267)
{0xf1d8, 0xe010, Operation::ROXRb, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xf1d8, 0xe050, Operation::ROXRw, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xf1d8, 0xe090, Operation::ROXRl, Decoder::ASLR_LSLR_ROLR_ROXLRr}, // 4-163 (p267)
{0xffc0, 0xe4c0, Operation::ROXRm, Decoder::ASLR_LSLR_ROLR_ROXLRm}, // 4-163 (p267)
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
{0xffc0, 0x48c0, Operation::MOVEMtoMl, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4880, Operation::MOVEMtoMw, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4cc0, Operation::MOVEMtoRl, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4c80, Operation::MOVEMtoRw, Decoder::MOVEM}, // 4-128 (p232)
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
{0xf1f8, 0x0108, Operation::MOVEPtoRw, Decoder::MOVEP}, // 4-133 (p237)
{0xf1f8, 0x0148, Operation::MOVEPtoRl, Decoder::MOVEP}, // 4-133 (p237)
{0xf1f8, 0x0188, Operation::MOVEPtoMw, Decoder::MOVEP}, // 4-133 (p237)
{0xf1f8, 0x01c8, Operation::MOVEPtoMl, Decoder::MOVEP}, // 4-133 (p237)
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
{0xffc0, 0x4a00, Operation::TSTb, Decoder::TST}, // 4-192 (p296)
{0xffc0, 0x4a40, Operation::TSTw, Decoder::TST}, // 4-192 (p296)
{0xffc0, 0x4a80, Operation::TSTl, Decoder::TST}, // 4-192 (p296)
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
{0xf1c0, 0xc0c0, Operation::MULU, Decoder::MULU_MULS}, // 4-139 (p243)
{0xf1c0, 0xc1c0, Operation::MULS, Decoder::MULU_MULS}, // 4-136 (p240)
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
{0xf1c0, 0x80c0, Operation::DIVU, Decoder::DIVU_DIVS}, // 4-97 (p201)
{0xf1c0, 0x81c0, Operation::DIVS, Decoder::DIVU_DIVS}, // 4-93 (p197)
Implements MOVE to/from USP.
2019-04-17 20:58:59 +00:00
{0xfff0, 0x4e60, Operation::MOVEAl, Decoder::MOVEUSP}, // 6-21 (p475)
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
{0xfff0, 0x4e40, Operation::TRAP, Decoder::TRAP}, // 4-188 (p292)
Takes a run at TRAPV. ... to leave 1466 as the unimplemented count.
2019-04-28 19:52:58 +00:00
{0xffff, 0x4e76, Operation::TRAPV, Decoder::TRAPV}, // 4-191 (p295)
Attempts an implementation of CHK. 1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 19:47:21 +00:00
{0xf1c0, 0x4180, Operation::CHK, Decoder::CHK}, // 4-69 (p173)
Makes an attempt at RTE and RTR.
2019-04-19 00:50:58 +00:00
{0xffff, 0x4e77, Operation::RTE_RTR, Decoder::RTE_RTR}, // 4-168 (p272) [RTR]
{0xffff, 0x4e73, Operation::RTE_RTR, Decoder::RTE_RTR}, // 6-84 (p538) [RTE]
Adds the official NOP. Which is a freebie.
2019-04-19 03:46:01 +00:00
{0xffff, 0x4e71, Operation::None, Decoder::NOP}, // 8-13 (p469)
Implements EXG and SWAP.
2019-04-19 15:27:43 +00:00
{0xf1f8, 0xc140, Operation::EXG, Decoder::EXG}, // 4-105 (p209)
{0xf1f8, 0xc148, Operation::EXG, Decoder::EXG}, // 4-105 (p209)
{0xf1f8, 0xc188, Operation::EXG, Decoder::EXG}, // 4-105 (p209)
Implements EXT.
2019-04-25 22:22:19 +00:00
{0xfff8, 0x4840, Operation::SWAP, Decoder::EXT_SWAP}, // 4-185 (p289)
Implements ANDI/ORI/EOR to SR/CCR.
2019-04-24 21:38:59 +00:00
{0xffff, 0x027c, Operation::ANDItoSR, Decoder::EORI_ORI_ANDI_SR},
{0xffff, 0x023c, Operation::ANDItoCCR, Decoder::EORI_ORI_ANDI_SR},
{0xffff, 0x0a7c, Operation::EORItoSR, Decoder::EORI_ORI_ANDI_SR},
{0xffff, 0x0a3c, Operation::EORItoCCR, Decoder::EORI_ORI_ANDI_SR},
{0xffff, 0x007c, Operation::ORItoSR, Decoder::EORI_ORI_ANDI_SR},
{0xffff, 0x003c, Operation::ORItoCCR, Decoder::EORI_ORI_ANDI_SR},
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
{0xf1c0, 0x0140, Operation::BCHGb, Decoder::BCHG_BSET}, // 4-28 (p132)
{0xffc0, 0x0840, Operation::BCHGb, Decoder::BCHG_BSET}, // 4-29 (p133)
{0xf1c0, 0x01c0, Operation::BSETb, Decoder::BCHG_BSET}, // 4-57 (p161)
{0xffc0, 0x08c0, Operation::BSETb, Decoder::BCHG_BSET}, // 4-58 (p162)
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
{0xffc0, 0x4ac0, Operation::TAS, Decoder::TAS}, // 4-186 (p290)
Implements EXT.
2019-04-25 22:22:19 +00:00
{0xfff8, 0x4880, Operation::EXTbtow, Decoder::EXT_SWAP}, // 4-106 (p210)
{0xfff8, 0x48c0, Operation::EXTwtol, Decoder::EXT_SWAP}, // 4-106 (p210)
Implements LINK and UNLINK. Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against. Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 21:12:31 +00:00
{0xfff8, 0x4e50, Operation::LINK, Decoder::LINK}, // 4-111 (p215)
{0xfff8, 0x4e58, Operation::UNLINK, Decoder::UNLINK}, // 4-194 (p298)
It leads to a TODO, but implemented decoding and initial setup of STOPpages.
2019-04-29 23:30:00 +00:00
{0xffff, 0x4e72, Operation::STOP, Decoder::STOP}, // 6-85 (p539)
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
};
std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
// The arbitrary_base is used so that the offsets returned by assemble_program into
// storage_.all_bus_steps_ can be retained and mapped into the final version of
// storage_.all_bus_steps_ at the end.
BusStep arbitrary_base;
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
#define op(...) storage_.all_micro_ops_.emplace_back(__VA_ARGS__)
#define seq(...) &arbitrary_base + assemble_program(__VA_ARGS__)
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
#define ea(n) &storage_.effective_address_[n].full
#define a(n) &storage_.address_[n].full
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
Completes conversion away from magic constants.
2019-04-12 19:48:29 +00:00
#define bw(x) (x)
#define l(x) (0x10000 | (x))
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
// Perform a linear search of the mappings above for this instruction.
Reverses order of instruction instantiation, reducing total bus step heft by about 11%. ... since that means inserting more complicated instructions before simpler ones in general, making subset finds more likely.
2019-04-30 02:20:18 +00:00
for(ssize_t instruction = 65535; instruction >= 0; --instruction) {
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
#ifndef NDEBUG
int hits = 0;
#endif
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
for(const auto &mapping: mappings) {
if((instruction & mapping.mask) == mapping.value) {
Implements MOVEA as distinct from MOVE. At least as far as MOVE is implemented, that is.
2019-03-22 23:25:53 +00:00
auto operation = mapping.operation;
Attempts properly to honour the bus-op and microcycle contract.
2019-03-17 02:36:09 +00:00
const auto micro_op_start = storage_.all_micro_ops_.size();
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
// The following fields are used commonly enough to be worth pulling out here.
Implements CMP.
2019-04-06 14:41:19 +00:00
const int ea_register = instruction & 7;
const int ea_mode = (instruction >> 3) & 7;
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
const int data_register = (instruction >> 9) & 7;
const int op_mode = (instruction >> 6)&7;
const bool op_mode_high_bit = !!(op_mode&4);
// These are almost always true; they're non-const so that they can be corrected
// by the few deviations.
bool is_byte_access = (op_mode&3) == 0;
bool is_long_word_access = (op_mode&3) == 2;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
Further fixes PEA, and OR/AND/EOR Dn, (An).
2019-05-29 18:37:15 +00:00
// if(instruction == 0xbd50) {
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
// printf("");
// }
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
#define dec(n) decrement_action(is_long_word_access, is_byte_access, n)
#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
Corrects direction of MOVE [to/from] USP.
2019-04-20 02:41:06 +00:00
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
switch(mapping.decoder) {
It leads to a TODO, but implemented decoding and initial setup of STOPpages.
2019-04-29 23:30:00 +00:00
case Decoder::STOP: {
storage_.instructions[instruction].requires_supervisor = true;
op(Action::None, seq("n"));
op(Action::PerformOperation);
} break;
Implements LINK and UNLINK. Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against. Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 21:12:31 +00:00
case Decoder::LINK: {
storage_.instructions[instruction].set_source(storage_, An, ea_register);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
} break;
case Decoder::UNLINK: {
storage_.instructions[instruction].set_destination(storage_, An, ea_register);
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
op(Action::PerformOperation);
} break;
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
case Decoder::TAS: {
const int mode = combined_mode(ea_mode, ea_register);
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
switch(mode) {
default: continue;
case Dn: // TAS Dn
op(Action::PerformOperation, seq("np"));
break;
case Ind: // TAS (An)
case PostInc: // TAS (An)+
op(Action::None, seq("nrd", { a(ea_register) }, false));
op(Action::PerformOperation, seq("tas np", { a(ea_register) }, false));
if(mode == PostInc) {
op(byte_inc(ea_register) | MicroOp::DestinationMask);
}
break;
case PreDec: // TAS -(An)
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd", { a(ea_register) }, false));
op(Action::PerformOperation, seq("tas np", { a(ea_register) }, false));
break;
case XXXl: // TAS (xxx).l
op(Action::None, seq("np"));
case XXXw: // TAS (xxx).w
case d16An: // TAS (d16, An)
case d8AnXn: // TAS (d8, An, Xn)
Corrects calculated-address TAS.
2019-04-25 16:42:05 +00:00
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq("np nrd", { ea(1) }, false));
Takes a run at TAS, clarifying bus cycles.
2019-04-25 16:19:40 +00:00
op(Action::PerformOperation, seq("tas np", { ea(1) }, false));
break;
}
} break;
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
case Decoder::BCHG_BSET: {
const int mode = combined_mode(ea_mode, ea_register);
// Operations on a register are .l; all others are the default .b.
if(ea_mode == Dn) {
operation = (operation == Operation::BSETb) ? Operation::BSETl : Operation::BCHGl;
}
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
if(instruction & 0x100) {
// The bit is nominated by a register.
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_source(storage_, Dn, data_register);
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
} else {
// The bit is nominated by a constant, that will be obtained right here.
storage_.instructions[instruction].set_source(storage_, Imm, 0);
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
}
switch(mode) {
default: continue;
case Dn: // [BCHG/BSET].l Dn, Dn
// Execution length depends on the selected bit, so allow flexible time for that.
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("r"));
break;
case Ind: // [BCHG/BSET].b Dn, (An)
case PostInc: // [BCHG/BSET].b Dn, (An)+
op(Action::None, seq("nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, false));
if(mode == PostInc) {
op(byte_inc(ea_register) | MicroOp::DestinationMask);
}
break;
case PreDec: // [BCHG/BSET].b Dn, -(An)
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, false));
break;
case XXXl: // [BCHG/BSET].b Dn, (xxx).l
op(Action::None, seq("np"));
case XXXw: // [BCHG/BSET].b Dn, (xxx).w
case d16An: // [BCHG/BSET].b Dn, (d16, An)
case d8AnXn: // [BCHG/BSET].b Dn, (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd np", mode), { ea(1) }, false));
op(Action::PerformOperation, seq("nw", { ea(1) }, false));
break;
}
} break;
Implements ANDI/ORI/EOR to SR/CCR.
2019-04-24 21:38:59 +00:00
case Decoder::EORI_ORI_ANDI_SR: {
// The source used here is always the high word of the prefetch queue.
storage_.instructions[instruction].requires_supervisor = !(instruction & 0x40);
op(Action::None, seq("np nn nn"));
op(Action::PerformOperation, seq("np np"));
} break;
Implements EXT.
2019-04-25 22:22:19 +00:00
case Decoder::EXT_SWAP: {
Implements EXG and SWAP.
2019-04-19 15:27:43 +00:00
storage_.instructions[instruction].set_destination(storage_, Dn, ea_register);
Causes SWAP actually to perform.
2019-04-24 17:06:12 +00:00
op(Action::PerformOperation, seq("np"));
Implements EXG and SWAP.
2019-04-19 15:27:43 +00:00
} break;
case Decoder::EXG: {
switch((instruction >> 3)&31) {
default: continue;
case 0x08:
storage_.instructions[instruction].set_source(storage_, Dn, data_register);
storage_.instructions[instruction].set_destination(storage_, Dn, ea_register);
break;
case 0x09:
storage_.instructions[instruction].set_source(storage_, An, data_register);
storage_.instructions[instruction].set_destination(storage_, An, ea_register);
break;
case 0x11:
storage_.instructions[instruction].set_source(storage_, Dn, data_register);
storage_.instructions[instruction].set_destination(storage_, An, ea_register);
break;
}
Causes EXG to function.
2019-04-24 20:32:16 +00:00
op(Action::PerformOperation, seq("np"));
Implements EXG and SWAP.
2019-04-19 15:27:43 +00:00
} break;
Adds the official NOP. Which is a freebie.
2019-04-19 03:46:01 +00:00
case Decoder::NOP: {
op(Action::None, seq("np"));
} break;
Makes an attempt at RTE and RTR.
2019-04-19 00:50:58 +00:00
case Decoder::RTE_RTR: {
storage_.instructions[instruction].requires_supervisor = instruction == 0x4e73;
// TODO: something explicit to ensure the nR nr nr is exclusively linked.
op(Action::PrepareRTE_RTR, seq("nR nr nr", { &storage_.precomputed_addresses_[0], &storage_.precomputed_addresses_[1], &storage_.precomputed_addresses_[2] } ));
op(Action::PerformOperation, seq("np np"));
op();
} break;
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
case Decoder::AND_OR_EOR: {
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
const bool to_ea = op_mode_high_bit;
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
const bool is_eor = (instruction >> 12) == 0xb;
// Weed out illegal operation modes.
if(op_mode == 7) continue;
const int mode = combined_mode(ea_mode, ea_register);
if(to_ea) {
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
storage_.instructions[instruction].set_source(storage_, Dn, data_register);
// Only EOR takes Dn as a destination effective address.
if(!is_eor && mode == Dn) continue;
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
case bw(Dn): // EOR.bw Dn, Dn
op(Action::PerformOperation, seq("np"));
break;
case l(Dn): // EOR.l Dn, Dn
op(Action::PerformOperation, seq("np nn"));
break;
case bw(Ind): // [AND/OR/EOR].bw Dn, (An)
case bw(PostInc): // [AND/OR/EOR].bw Dn, (An)+
Further fixes PEA, and OR/AND/EOR Dn, (An).
2019-05-29 18:37:15 +00:00
op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::DestinationMask);
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
}
break;
case bw(PreDec): // [AND/OR/EOR].bw Dn, -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(ea_register) | MicroOp::SourceMask, seq("n nrd", { a(ea_register) }, !is_byte_access));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
break;
case l(PreDec): // [AND/OR/EOR].l Dn, -(An)
op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("n"));
Corrects decoding of AND/OR x, Dn.
2019-04-25 18:19:13 +00:00
case l(Ind): // [AND/OR/EOR].l Dn, (An)
case l(PostInc): // [AND/OR/EOR].l Dn, (An)+
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) }));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
break;
case bw(XXXl): // [AND/OR/EOR].bw Dn, (xxx).l
op(Action::None, seq("np"));
case bw(XXXw): // [AND/OR/EOR].bw Dn, (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(d16An): // [AND/OR/EOR].bw Dn, (d16, An)
case bw(d8AnXn): // [AND/OR/EOR].bw Dn, (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd", mode), { ea(1) }, !is_byte_access));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np nw", { ea(1) }, !is_byte_access));
break;
case l(XXXl): // [AND/OR/EOR].l Dn, (xxx).l
op(Action::None, seq("np"));
case l(XXXw): // [AND/OR/EOR].l Dn, (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(d16An): // [AND/OR/EOR].l Dn, (d16, An)
case l(d8AnXn): // [AND/OR/EOR].l Dn, (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nRd+ nrd", mode), { ea(1), ea(1) }));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) }));
break;
}
} else {
// EORs can be to EA only.
if(is_eor) continue;
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
Corrects decoding of AND/OR x, Dn.
2019-04-25 18:19:13 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
default: continue;
case bw(Dn): // [AND/OR].bw Dn, Dn
op(Action::PerformOperation, seq("np"));
break;
case l(Dn): // [AND/OR].l Dn, Dn
op(Action::PerformOperation, seq("np nn"));
break;
case bw(Ind): // [AND/OR].bw (An), Dn
case bw(PostInc): // [AND/OR].bw (An)+, Dn
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np"));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::SourceMask);
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
}
break;
case bw(PreDec): // [AND/OR].bw -(An), Dn
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(ea_register) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np"));
break;
case l(PreDec): // [AND/OR].l -(An), Dn
op(int(Action::Decrement4) | MicroOp::SourceMask, seq("n"));
case l(Ind): // [AND/OR].l (An), Dn,
case l(PostInc): // [AND/OR].l (An)+, Dn
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq("np n"));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::SourceMask);
}
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXl): // [AND/OR].bw (xxx).l, Dn
op(Action::None, seq("np"));
case bw(XXXw): // [AND/OR].bw (xxx).w, Dn
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
case bw(d16An): // [AND/OR].bw (d16, An), Dn
case bw(d16PC): // [AND/OR].bw (d16, PC), Dn
case bw(d8AnXn): // [AND/OR].bw (d8, An, Xn), Dn
case bw(d8PCXn): // [AND/OR].bw (d8, PX, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nr", mode), { ea(0) }, !is_byte_access));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np"));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // [AND/OR].bw (xxx).l, Dn
op(Action::None, seq("np"));
case l(XXXw): // [AND/OR].bw (xxx).w, Dn
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
case l(d16An): // [AND/OR].l (d16, An), Dn
case l(d16PC): // [AND/OR].l (d16, PC), Dn
case l(d8AnXn): // [AND/OR].l (d8, An, Xn), Dn
case l(d8PCXn): // [AND/OR].l (d8, PX, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nR+ nr", mode), { ea(0), ea(0) }));
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
op(Action::PerformOperation, seq("np n"));
break;
case bw(Imm): // [AND/OR].bw #, Dn
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op(Action::PerformOperation, seq("np"));
break;
case l(Imm): // [AND/OR].l #, Dn
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op(Action::PerformOperation, seq("np nn"));
break;
}
}
} break;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case Decoder::DIVU_DIVS: {
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
case Dn: // [DIVU/DIVS] Dn, Dn
op(Action::PerformOperation, seq("r"));
op(Action::None, seq("np"));
break;
case Ind: // [DIVU/DIVS] (An), Dn
case PostInc: // [DIVU/DIVS] (An)+, Dn
op(Action::None, seq("nr", { a(ea_register) }));
op(Action::PerformOperation, seq("r np"));
if(mode == PostInc) {
op(int(Action::Increment2) | MicroOp::SourceMask);
}
break;
case PreDec: // [DIVU/DIVS] -(An), Dn
op(int(Action::Decrement2) | MicroOp::SourceMask, seq("nr", { a(ea_register) }));
op(Action::PerformOperation, seq("r np"));
break;
case XXXl: // [DIVU/DIVS] (XXX).l, Dn
op(Action::None, seq("np"));
case XXXw: // [DIVU/DIVS] (XXX).w, Dn
case d16An: // [DIVU/DIVS] (d16, An), Dn
case d16PC: // [DIVU/DIVS] (d16, PC), Dn
case d8AnXn: // [DIVU/DIVS] (d8, An, Xn), Dn
case d8PCXn: // [DIVU/DIVS] (d8, PC, Xn), Dn
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq("np nr", { ea(0) }));
op(Action::PerformOperation, seq("r np"));
break;
case Imm: // [DIVU/DIVS] #, Dn
// DEVIATION FROM YACHT.TXT. It shows an additional np, which is incorrect.
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op(Action::PerformOperation, seq("r np"));
break;
}
} break;
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
case Decoder::MULU_MULS: {
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case Dn: // [MULU/MULS] Dn, Dn
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("r"));
break;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case Ind: // [MULU/MULS] (An), Dn
case PostInc: // [MULU/MULS] (An)+, Dn
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(Action::None, seq("nr np", { a(ea_register) }));
op(Action::PerformOperation, seq("r"));
if(mode == PostInc) {
op(int(Action::Increment2) | MicroOp::SourceMask);
}
break;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case PreDec: // [MULU/MULS] -(An), Dn
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(int(Action::Decrement2) | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }));
op(Action::PerformOperation, seq("r"));
break;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case XXXl: // [MULU/MULS] (XXX).l, Dn
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(Action::None, seq("np"));
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case XXXw: // [MULU/MULS] (XXX).w, Dn
case d16An: // [MULU/MULS] (d16, An), Dn
case d16PC: // [MULU/MULS] (d16, PC), Dn
case d8AnXn: // [MULU/MULS] (d8, An, Xn), Dn
case d8PCXn: // [MULU/MULS] (d8, PX, Xn), Dn
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("n np nr np", mode), { ea(0) }));
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(Action::PerformOperation, seq("r"));
break;
Attempts DIVU and DIVS. Reportedly leaving 10965 operations now unimplemented.
2019-04-27 02:22:35 +00:00
case Imm: // [MULU/MULS] #, Dn
// DEVIATION FROM YACHT.TXT. It shows an additional np, which is incorrect.
Shortens impact of MULU on the instruction stream to correct parsing. I need to look into this.
2019-04-17 19:15:48 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Implements MULU and MULS.
2019-04-17 02:16:43 +00:00
op(Action::PerformOperation, seq("r"));
break;
}
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::EORI_ORI_ANDI_SUBI_ADDI: {
const int mode = combined_mode(ea_mode, ea_register);
// Source is always something cribbed from the instruction stream;
// destination is going to be in the write address unit.
storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
if(mode == Dn) {
storage_.instructions[instruction].destination = &storage_.data_[ea_register];
} else {
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
storage_.instructions[instruction].destination_address = &storage_.address_[ea_register];
}
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case bw(Dn): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, Dn
Resolves additional byte accesses being signalled as word.
2019-04-24 01:23:20 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(Action::PerformOperation);
break;
Resolves additional byte accesses being signalled as word.
2019-04-24 01:23:20 +00:00
case l(Dn): // [EORI/ORI/ANDI/SUBI/ADDI].l #, Dn
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(Action::None, seq("np"));
Resolves additional byte accesses being signalled as word.
2019-04-24 01:23:20 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np nn"));
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(Action::PerformOperation);
break;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case bw(Ind): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (An)
case bw(PostInc): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (An)+
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::DestinationMask);
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
}
break;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case l(Ind): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (An)
case l(PostInc): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (An)+
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
op( int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np nRd+ nrd np", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
break;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case bw(PreDec): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(ea_register) | MicroOp::DestinationMask);
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np n nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
break;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case l(PreDec): // [EORI/ORI/ANDI/SUBI/ADDI].l #, -(An)
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(int(Action::Decrement4) | MicroOp::DestinationMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
op( int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np n nRd+ nrd np", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXw): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).w
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case bw(d8AnXn): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (d8, An, Xn)
case bw(d16An): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (d16, An)
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXw): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (xxx).w
Completes addressing modes for ADDI/etc/etc.
2019-04-17 01:34:16 +00:00
case l(d8AnXn): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (d8, An, Xn)
case l(d16An): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (d16, An)
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Completes addressing modes for ADDI/etc/etc.
2019-04-17 01:34:16 +00:00
seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
Consolidates JSR and BSR preparation.
2019-04-17 01:29:37 +00:00
case bw(XXXl): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).l
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nrd np", { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
Completes addressing modes for ADDI/etc/etc.
2019-04-17 01:34:16 +00:00
case l(XXXl): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (xxx).l
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nRd+ nrd np", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
}
} break;
case Decoder::ADD_SUB: {
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
// ADD and SUB definitely always involve a data register and an arbitrary addressing mode;
// which direction they operate in depends on bit 8.
const bool reverse_source_destination = !(instruction & 256);
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
if(reverse_source_destination) {
storage_.instructions[instruction].destination = &storage_.data_[data_register];
storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source_address = &storage_.address_[ea_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
// Perform [ADD/SUB].blw <ea>, Dn
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Dn): // ADD/SUB.bw Dn, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.data_[ea_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation, seq("np"));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Dn): // ADD/SUB.l Dn, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.data_[ea_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation, seq("np nn"));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(An): // ADD/SUB.bw An, Dn
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
// Address registers can't provide single bytes.
if(is_byte_access) continue;
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.address_[ea_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation, seq("np"));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(An): // ADD/SUB.l An, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.address_[ea_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation, seq("np nn"));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Ind): // ADD/SUB.bw (An), Dn
case bw(PostInc): // ADD/SUB.bw (An)+, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::None, seq("nr np", { a(ea_register) }, !is_byte_access));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
if(ea_mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::SourceMask);
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
}
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Ind): // ADD/SUB.l (An), Dn
case l(PostInc): // ADD/SUB.l (An)+, Dn
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
seq("nR+ nr np n", { ea(0), ea(0) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(int(Action::Increment4) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(PreDec): // ADD/SUB.bw -(An), Dn
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op( dec(ea_register) | MicroOp::SourceMask,
Implements CMP.
2019-04-06 14:41:19 +00:00
seq("n nr np", { a(ea_register) }, !is_byte_access));
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(PreDec): // ADD/SUB.l -(An), Dn
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::Decrement4) | MicroOp::SourceMask);
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
seq("n nR+ nr np n", { ea(0), ea(0) }));
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(XXXl): // ADD/SUB.bw (xxx).l, Dn
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::None, seq("np"));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(XXXw): // ADD/SUB.bw (xxx).w, Dn
case bw(d16PC): // ADD/SUB.bw (d16, PC), Dn
case bw(d8PCXn): // ADD/SUB.bw (d8, PC, Xn), Dn
case bw(d16An): // ADD/SUB.bw (d16, An), Dn
case bw(d8AnXn): // ADD/SUB.bw (d8, An, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
seq(pseq("np nr np", mode), { ea(0) }, !is_byte_access));
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // ADD/SUB.l (xxx).l, Dn
op(Action::None, seq("np"));
case l(XXXw): // ADD/SUB.l (xxx).w, Dn
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(d16PC): // ADD/SUB.l (d16, PC), Dn
case l(d8PCXn): // ADD/SUB.l (d8, PC, Xn), Dn
case l(d16An): // ADD/SUB.l (d16, An), Dn
case l(d8AnXn): // ADD/SUB.l (d8, An, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
seq(pseq("np nR+ nr np n", mode), { ea(0), ea(0) }));
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Imm): // ADD/SUB.bw #, Dn
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Imm): // ADD/SUB.l #, Dn
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::None, seq("np"));
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np nn"));
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
op(Action::PerformOperation);
break;
}
} else {
storage_.instructions[instruction].source = &storage_.data_[data_register];
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const auto destination_register = ea_register;
Fixes ADD/SUB Dn,x to use the proper destination value.
2019-04-17 14:23:47 +00:00
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
storage_.instructions[instruction].destination_address = &storage_.address_[destination_register];
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
// Perform [ADD/SUB].blw Dn, <ea>
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Ind): // ADD/SUB.bw Dn, (An)
case bw(PostInc): // ADD/SUB.bw Dn, (An)+
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
op(Action::None, seq("nrd np", { a(destination_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(destination_register) }, !is_byte_access));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
if(ea_mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(destination_register) | MicroOp::DestinationMask);
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
}
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Ind): // ADD/SUB.l Dn, (An)
case l(PostInc): // ADD/SUB.l Dn, (An)+
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
if(ea_mode == PostInc) {
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
break;
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(PreDec): // ADD/SUB.bw Dn, -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op( dec(destination_register) | MicroOp::DestinationMask,
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
seq("n nrd np", { a(destination_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(destination_register) }, !is_byte_access));
break;
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(PreDec): // ADD/SUB.l Dn, -(An)
Completes ADD and SUB.
2019-04-04 01:41:59 +00:00
op( int(Action::Decrement4) | MicroOp::DestinationMask);
op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask,
seq("n nRd+ nrd np", { ea(1), ea(1) }));
op( Action::PerformOperation,
seq("nw- nW", { ea(1), ea(1) }));
break;
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXl): // ADD/SUB.bw Dn, (xxx).l
op(Action::None, seq("np"));
case bw(XXXw): // ADD/SUB.bw Dn, (xxx).w
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(d16An): // ADD/SUB.bw (d16, An), Dn
case bw(d8AnXn): // ADD/SUB.bw (d8, An, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // ADD/SUB.l Dn, (xxx).l
op(Action::None, seq("np"));
case l(XXXw): // ADD/SUB.l Dn, (xxx).w
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(d16An): // ADD/SUB.l (d16, An), Dn
case l(d8AnXn): // ADD/SUB.l (d8, An, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
}
}
} break;
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::ADDA_SUBA: {
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_destination(storage_, 1, data_register);
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
is_long_word_access = op_mode_high_bit;
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Dn): // ADDA/SUBA.w Dn, An
case bw(An): // ADDA/SUBA.w An, An
case l(Dn): // ADDA/SUBA.l Dn, An
case l(An): // ADDA/SUBA.l An, An
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(Action::PerformOperation, seq("np nn"));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Ind): // ADDA/SUBA.w (An), An
case bw(PostInc): // ADDA/SUBA.w (An)+, An
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::None, seq("nr np nn", { a(ea_register) }));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
if(ea_mode == PostInc) {
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::Increment2) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Ind): // ADDA/SUBA.l (An), An
case l(PostInc): // ADDA/SUBA.l (An)+, An
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr np n", { ea(0), ea(0) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::Increment4) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(PreDec): // ADDA/SUBA.w -(An), An
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::Decrement2) | MicroOp::SourceMask);
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::None, seq("n nr np nn", { a(ea_register) }));
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(PreDec): // ADDA/SUBA.l -(An), An
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::Decrement4) | MicroOp::SourceMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("n nR+ nr np n", { ea(0), ea(0) }));
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXl): // ADDA/SUBA.w (xxx).l, An
op(Action::None, seq("np"));
case bw(XXXw): // ADDA/SUBA.w (xxx).w, An
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(d16An): // ADDA/SUBA.w (d16, An), An
case bw(d8AnXn): // ADDA/SUBA.w (d8, An, Xn), An
Adds missing addressing modes for ADDA and SUBA. ... reducing missing opcodes to 1941.
2019-04-27 21:22:26 +00:00
case bw(d16PC): // ADDA/SUBA.w (d16, PC), An
case bw(d8PCXn): // ADDA/SUBA.w (d8, PC, Xn), An
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
Corrects EA usage for ADDA and SUBA.
2019-04-20 03:02:41 +00:00
seq(pseq("np nr np nn", mode), { ea(0) }));
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // ADDA/SUBA.l (xxx).l, An
op(Action::None, seq("np"));
case l(XXXw): // ADDA/SUBA.l (xxx).w, An
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(d16An): // ADDA/SUBA.l (d16, An), An
case l(d8AnXn): // ADDA/SUBA.l (d8, An, Xn), An
Adds missing addressing modes for ADDA and SUBA. ... reducing missing opcodes to 1941.
2019-04-27 21:22:26 +00:00
case l(d16PC): // ADDA/SUBA.l (d16, PC), An
case l(d8PCXn): // ADDA/SUBA.l (d8, PC, Xn), An
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
Corrects EA usage for ADDA and SUBA.
2019-04-20 03:02:41 +00:00
seq(pseq("np nR+ nr np n", mode), { ea(0), ea(0) }));
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case bw(Imm): // ADDA/SUBA.w #, An
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np nn"));
op(Action::PerformOperation);
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case l(Imm): // ADDA/SUBA.l #, Dn
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np nn"));
op(Action::PerformOperation);
break;
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-03 01:50:58 +00:00
}
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::ADDQ_SUBQ: {
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
ADD/SUBQ #, An shouldn't set flags. Also, temporarily at least, adds a new means for observing CPU behaviour.
2019-04-24 13:59:54 +00:00
// If the destination is an address register then byte mode isn't allowed, and
// flags shouldn't be affected (so, a different operation is used).
if(mode == An) {
if(is_byte_access) continue;
switch(operation) {
default: break;
case Operation::ADDQl: // TODO: should the adds be distinguished? If so, how?
case Operation::ADDQw: operation = Operation::ADDQAl; break;
case Operation::SUBQl:
case Operation::SUBQw: operation = Operation::SUBQAl; break;
}
}
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
case bw(Dn): // [ADD/SUB]Q.bw #, Dn
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
op(Action::PerformOperation, seq("np"));
break;
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
case l(Dn): // [ADD/SUB]Q.l #, Dn
case l(An): // [ADD/SUB]Q.l #, An
case bw(An): // [ADD/SUB]Q.bw #, An
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
op(Action::PerformOperation, seq("np nn"));
break;
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
case bw(Ind): // [ADD/SUB]Q.bw #, (An)
case bw(PostInc): // [ADD/SUB]Q.bw #, (An)+
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
op(Action::None, seq("nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::DestinationMask);
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
}
break;
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
case l(PreDec): // [ADD/SUB]Q.l #, -(An)
op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("n"));
case l(Ind): // [ADD/SUB]Q.l #, (An)
case l(PostInc): // [ADD/SUB]Q.l #, (An)+
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
break;
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
case bw(PreDec): // [ADD/SUB]Q.bw #, -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op( dec(ea_register) | MicroOp::DestinationMask,
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
seq("n nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
break;
case bw(XXXl): // [ADD/SUB]Q.bw #, (xxx).l
op(Action::None, seq("np"));
case bw(XXXw): // [ADD/SUB]Q.bw #, (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(d16An): // [ADD/SUB]Q.bw #, (d16, An)
case bw(d8AnXn): // [ADD/SUB]Q.bw #, (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
case l(XXXl): // [ADD/SUB]Q.l #, (xxx).l
op(Action::None, seq("np"));
case l(XXXw): // [ADD/SUB]Q.l #, (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(d16An): // [ADD/SUB]Q.l #, (d16, An)
case l(d8AnXn): // [ADD/SUB]Q.l #, (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 18:28:31 +00:00
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 15:19:45 +00:00
}
} break;
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
case Decoder::ADDX_SUBX: {
if(instruction & 0x8) {
// Use predecrementing address registers.
storage_.instructions[instruction].set_source(storage_, Ind, ea_register);
storage_.instructions[instruction].set_destination(storage_, Ind, data_register);
if(is_long_word_access) {
// Access order is very atypical here: it's lower parts each for both words,
// and then also a lower-part-first write.
op(int(Action::Decrement2) | MicroOp::SourceMask | MicroOp::DestinationMask);
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask,
seq("n nr- nR nrd- nRd+", { ea(0), ea(0), ea(1), ea(1) }));
op(int(Action::Decrement2) | MicroOp::SourceMask | MicroOp::DestinationMask);
op(Action::PerformOperation, seq("nw- np nW", { ea(1), ea(1) }));
} else {
const int source_dec = dec(ea_register);
const int destination_dec = dec(data_register);
int first_action;
if(source_dec == destination_dec) {
first_action = int(Action::Decrement4) | MicroOp::SourceMask | MicroOp::DestinationMask;
} else {
op(source_dec | MicroOp::SourceMask);
first_action = destination_dec | MicroOp::DestinationMask;
}
op(first_action, seq("n nr nrd np", { ea(0), ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
}
} else {
// Use data registers.
storage_.instructions[instruction].set_source(storage_, Dn, ea_register);
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
if(is_long_word_access) {
op(Action::PerformOperation, seq("np nn"));
} else {
op(Action::PerformOperation, seq("np"));
}
}
} break;
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
// This decoder actually decodes nothing; it just schedules a PerformOperation followed by an empty step.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::Bcc_BSR: {
Implements (arguably: fixes) BSR.
2019-04-16 03:20:36 +00:00
const int condition = (instruction >> 8) & 0xf;
if(condition == 1) {
// This is BSR, which is unconditional and means pushing a return address to the stack first.
// Push the return address to the stack.
Mental delusion lifted: JSR doesn't look enough like BSR.
2019-04-17 14:02:14 +00:00
op(Action::PrepareBSR, seq("n nW+ nw", { ea(1), ea(1) }));
Implements (arguably: fixes) BSR.
2019-04-16 03:20:36 +00:00
}
// This is Bcc.
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
op(Action::PerformOperation);
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
op(); // The above looks terminal, but will be dynamically reprogrammed.
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
} break;
// A little artificial, there's nothing really to decode for BRA.
case Decoder::BRA: {
op(Action::PerformOperation, seq("n np np"));
} break;
Implements BCLR.
2019-04-15 22:11:02 +00:00
// Decodes a BTST, potential mutating the operation into a BTSTl,
// or a BCLR.
case Decoder::BCLR:
Adds BTST.
2019-04-05 01:43:22 +00:00
case Decoder::BTST: {
Implements BCLR.
2019-04-15 22:11:02 +00:00
const bool is_bclr = mapping.decoder == Decoder::BCLR;
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_source(storage_, 0, data_register);
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
Adds BTST.
2019-04-05 01:43:22 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Adds BTST.
2019-04-05 01:43:22 +00:00
switch(mode) {
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case Dn: // BTST.l Dn, Dn
Implements BCLR.
2019-04-15 22:11:02 +00:00
if(is_bclr) {
operation = Operation::BCLRl;
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("r"));
} else {
operation = Operation::BTSTl;
op(Action::PerformOperation, seq("np n"));
}
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case Ind: // BTST.b Dn, (An)
case PostInc: // BTST.b Dn, (An)+
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::None, seq("nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
op(byte_inc(ea_register) | MicroOp::DestinationMask);
Adds BTST.
2019-04-05 01:43:22 +00:00
}
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case PreDec: // BTST.b Dn, -(An)
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Implements a missing form of BTST.
2019-04-29 03:20:50 +00:00
case XXXl: // BTST.b Dn, (xxx).l
op(Action::None, seq("np"));
case XXXw: // BTST.b Dn, (xxx).w
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case d16An: // BTST.b Dn, (d16, An)
case d8AnXn: // BTST.b Dn, (d8, An, Xn)
case d16PC: // BTST.b Dn, (d16, PC)
case d8PCXn: // BTST.b Dn, (d8, PC, Xn)
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
// PC-relative addressing isn't support for BCLR.
if((mode == d16PC || mode == d8PCXn) && is_bclr) continue;
Implements a missing form of BTST.
2019-04-29 03:20:50 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Adds BTST.
2019-04-05 01:43:22 +00:00
seq(pseq("np nrd np", mode), { ea(1) }, false));
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Implements a missing form of BTST.
2019-04-29 03:20:50 +00:00
case Imm: // BTST.b Dn, #
if(is_bclr) continue;
/* Yacht.txt doesn't cover this; this is a guess. */
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
op(Action::PerformOperation, seq("np"));
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
}
} break;
Implements BCLR.
2019-04-15 22:11:02 +00:00
case Decoder::BCLRIMM:
Adds BTST.
2019-04-05 01:43:22 +00:00
case Decoder::BTSTIMM: {
Implements BCLR.
2019-04-15 22:11:02 +00:00
const bool is_bclr = mapping.decoder == Decoder::BCLRIMM;
Adds BTST.
2019-04-05 01:43:22 +00:00
storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
Adds BTST.
2019-04-05 01:43:22 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Adds BTST.
2019-04-05 01:43:22 +00:00
switch(mode) {
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case Dn: // BTST.l #, Dn
Implements BCLR.
2019-04-15 22:11:02 +00:00
if(is_bclr) {
operation = Operation::BCLRl;
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op(Action::PerformOperation, seq("r"));
} else {
operation = Operation::BTSTl;
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np n"));
op(Action::PerformOperation);
}
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case Ind: // BTST.b #, (An)
case PostInc: // BTST.b #, (An)+
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(ea_register) }, false));
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
op(byte_inc(ea_register) | MicroOp::DestinationMask);
Adds BTST.
2019-04-05 01:43:22 +00:00
}
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case PreDec: // BTST.b #, -(An)
Adds BTST.
2019-04-05 01:43:22 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Takes a run at BSET and BCHG.
2019-04-25 03:01:32 +00:00
op(byte_dec(ea_register) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }, false));
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::PerformOperation, is_bclr ? seq("nw", { a(ea_register) }, false) : nullptr);
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Improves carry/extend for ROXL and ROXR.
2019-05-07 01:14:16 +00:00
case XXXw: // BTST.b #, (xxx).w
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case d16An: // BTST.b #, (d16, An)
case d8AnXn: // BTST.b #, (d8, An, Xn)
case d16PC: // BTST.b #, (d16, PC)
case d8PCXn: // BTST.b #, (d8, PC, Xn)
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
// PC-relative addressing isn't support for BCLR.
if((mode == d16PC || mode == d8PCXn) && is_bclr) continue;
Adds BTST.
2019-04-05 01:43:22 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Adds BTST.
2019-04-05 01:43:22 +00:00
seq(pseq("np nrd np", mode), { ea(1) }, false));
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case XXXl: // BTST.b #, (xxx).l
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Adds BTST.
2019-04-05 01:43:22 +00:00
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nrd np", { ea(1) }, false));
Implements BCLR.
2019-04-15 22:11:02 +00:00
op(Action::PerformOperation, is_bclr ? seq("nw", { ea(1) }, false) : nullptr);
Adds BTST.
2019-04-05 01:43:22 +00:00
break;
}
} break;
Implements all `MOVE Dn, Dn`.
2019-03-17 03:14:18 +00:00
// Decodes the format used by ABCD and SBCD.
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::ABCD_SBCD: {
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
if(instruction & 8) {
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source_address = &storage_.address_[ea_register];
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].destination_address = &storage_.address_[data_register];
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
const int source_dec = dec(ea_register);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
const int destination_dec = dec(data_register);
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
int first_action = source_dec | MicroOp::SourceMask | MicroOp::DestinationMask;
if(source_dec != destination_dec) {
first_action = source_dec | MicroOp::SourceMask;
op(destination_dec | MicroOp::DestinationMask);
}
op( first_action,
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
seq("n nr nrd np nw", { a(ea_register), a(data_register), a(data_register) }, false));
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
op(Action::PerformOperation);
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
} else {
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.data_[ea_register];
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].destination = &storage_.data_[data_register];
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
op(Action::PerformOperation, seq("np n"));
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::ASLR_LSLR_ROLR_ROXLRr: {
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
storage_.instructions[instruction].set_destination(storage_, 0, ea_register);
Implements the fixed part of register shifts.
2019-04-10 02:12:37 +00:00
// All further decoding occurs at runtime; that's also when the proper number of
// no-op cycles will be scheduled.
if(((instruction >> 6) & 3) == 2) {
op(Action::None, seq("np nn"));
} else {
op(Action::None, seq("np n"));
}
Implements ASL, ASR, LSL and LSR.
2019-04-11 02:31:04 +00:00
// Use a no-op bus cycle that can have its length filled in later.
op(Action::PerformOperation, seq("r"));
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::ASLR_LSLR_ROLR_ROXLRm: {
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
default: continue;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case Ind: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (An)
case PostInc: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (An)+
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
op(Action::None, seq("nrd np", { a(ea_register) }));
op(Action::PerformOperation, seq("nw", { a(ea_register) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(ea_mode == PostInc) {
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
op(int(Action::Increment2) | MicroOp::DestinationMask);
}
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case PreDec: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w -(An)
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
op(int(Action::Decrement2) | MicroOp::DestinationMask, seq("n nrd np", { a(ea_register) }));
op(Action::PerformOperation, seq("nw", { a(ea_register) }));
break;
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case XXXl: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (xxx).l
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
op(Action::None, seq("np"));
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
case XXXw: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case d16An: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (d16, An)
case d8AnXn: // AS(L/R)/LS(L/R)/RO(L/R)/ROX(L/R).w (d8, An, Xn)
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
seq(pseq("np nrd np", mode), { ea(1) }));
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-10 01:48:08 +00:00
op(Action::PerformOperation, seq("nw", { ea(1) }));
break;
}
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::CLR_NEG_NEGX_NOT: {
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
default: continue;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Dn): // [CLR/NEG/NEGX/NOT].bw Dn
case l(Dn): // [CLR/NEG/NEGX/NOT].l Dn
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(Action::PerformOperation, seq("np"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Ind): // [CLR/NEG/NEGX/NOT].bw (An)
case bw(PostInc): // [CLR/NEG/NEGX/NOT].bw (An)+
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(ea_mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::DestinationMask);
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
}
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Ind): // [CLR/NEG/NEGX/NOT].l (An)
case l(PostInc): // [CLR/NEG/NEGX/NOT].l (An)+
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(ea_mode == PostInc) {
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(PreDec): // [CLR/NEG/NEGX/NOT].bw -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op( dec(ea_register) | MicroOp::DestinationMask,
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
seq("nrd", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(PreDec): // [CLR/NEG/NEGX/NOT].l -(An)
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(int(Action::Decrement4) | MicroOp::DestinationMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask,
seq("n nRd+ nrd", { ea(1), ea(1) }));
op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) }));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXl): // [CLR/NEG/NEGX/NOT].bw (xxx).l
op(Action::None, seq("np"));
case bw(XXXw): // [CLR/NEG/NEGX/NOT].bw (xxx).w
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(d16An): // [CLR/NEG/NEGX/NOT].bw (d16, An)
case bw(d8AnXn): // [CLR/NEG/NEGX/NOT].bw (d8, An, Xn)
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
seq(pseq("np nrd", mode), { ea(1) }, !is_byte_access));
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(Action::PerformOperation, seq("np nw", { ea(1) }, !is_byte_access));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // [CLR/NEG/NEGX/NOT].l (xxx).l
op(Action::None, seq("np"));
case l(XXXw): // [CLR/NEG/NEGX/NOT].l (xxx).w
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(d16An): // [CLR/NEG/NEGX/NOT].l (d16, An)
case l(d8AnXn): // [CLR/NEG/NEGX/NOT].l (d8, An, Xn)
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
seq(pseq("np nRd+ nrd", mode), { ea(1), ea(1) }));
Implements CLR, NEG, NEGX and NOT.
2019-04-08 02:07:39 +00:00
op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) }));
break;
}
} break;
Implements CMP.
2019-04-06 14:41:19 +00:00
case Decoder::CMP: {
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].destination = &storage_.data_[data_register];
Corrects source/destination order of CMP setup.
2019-04-07 00:00:15 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Implements CMP.
2019-04-06 14:41:19 +00:00
// Byte accesses are not allowed with address registers.
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
if(is_byte_access && ea_mode == An) {
Implements CMP.
2019-04-06 14:41:19 +00:00
continue;
}
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(is_long_word_access ? l(mode) : bw(mode)) {
Implements CMP.
2019-04-06 14:41:19 +00:00
default: continue;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Dn): // CMP.bw Dn, Dn
case l(Dn): // CMP.l Dn, Dn
case bw(An): // CMP.w An, Dn
case l(An): // CMP.l An, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::PerformOperation, seq("np"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Ind): // CMP.bw (An), Dn
case bw(PostInc): // CMP.bw (An)+, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::None, seq("nr np", { a(ea_register) }, !is_byte_access));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::SourceMask);
Implements CMP.
2019-04-06 14:41:19 +00:00
}
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Ind): // CMP.l (An), Dn
case l(PostInc): // CMP.l (An)+, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr np n", { ea(0), ea(0) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Implements CMP.
2019-04-06 14:41:19 +00:00
op(int(Action::Increment4) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(PreDec): // CMP.bw -(An), Dn
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op( dec(ea_register) | MicroOp::SourceMask,
Implements CMP.
2019-04-06 14:41:19 +00:00
seq("n nr np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(PreDec): // CMP.l -(An), Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
op(int(Action::Decrement4) | MicroOp::SourceMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("n nR+ nr np n", { ea(0), ea(0) }));
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXl): // CMP.bw (xxx).l, Dn
op(Action::None, seq("np"));
case bw(XXXw): // CMP.bw (xxx).w, Dn
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(d16An): // CMP.bw (d16, An), Dn
case bw(d8AnXn): // CMP.bw (d8, An, Xn), Dn
case bw(d16PC): // CMP.bw (d16, PC), Dn
case bw(d8PCXn): // CMP.bw (d8, PC, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
seq(pseq("np nr np", mode), { ea(0) }, !is_byte_access));
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(XXXl): // CMP.l (xxx).l, Dn
op(Action::None, seq("np"));
case l(XXXw): // CMP.l (xxx).w, Dn
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(d16An): // CMP.l (d16, An), Dn
case l(d8AnXn): // CMP.l (d8, An, Xn), Dn
case l(d16PC): // CMP.l (d16, PC), Dn
case l(d8PCXn): // CMP.l (d8, PC, Xn), Dn
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::SourceMask,
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
seq(pseq("np nR+ nr np n", mode), { ea(0), ea(0) }));
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Imm): // CMP.br #, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
op(Action::PerformOperation, seq("np np"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Imm): // CMP.l #, Dn
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("np np n"));
break;
}
} break;
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
case Decoder::CMPA: {
Corrects decoding of CMPA.
2019-04-21 01:21:33 +00:00
// Only operation modes 011 and 111 are accepted, and long words are selected
// by the top bit.
if(((op_mode)&3) != 3) continue;
is_long_word_access = op_mode == 7;
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].destination = &storage_.address_[data_register];
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
const int mode = combined_mode(ea_mode, ea_register, true);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
switch(is_long_word_access ? l(mode) : bw(mode)) {
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
default: continue;
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
case bw(Dn): // CMPA.w [An/Dn], An
case l(Dn): // CMPA.l [An/Dn], An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(Action::PerformOperation, seq("np n"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Ind): // CMPA.w (An), An
case bw(PostInc): // CMPA.w (An)+, An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(Action::None, seq("nr", { a(ea_register) }));
op(Action::PerformOperation, seq("np n"));
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
if(mode == PostInc) {
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(int(Action::Increment2) | MicroOp::SourceMask);
}
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Ind): // CMPA.l (An), An
case l(PostInc): // CMPA.l (An)+, An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq("np n"));
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
if(mode == PostInc) {
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(int(Action::Increment4) | MicroOp::SourceMask);
}
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(PreDec): // CMPA.w -(An), An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(int(Action::Decrement2) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }));
op(Action::PerformOperation, seq("np n"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(PreDec): // CMPA.l -(An), An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(int(Action::Decrement4) | MicroOp::SourceMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq("np n"));
break;
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
case bw(XXXl): // CMPA.w (xxx).l, An
op(Action::None, seq("np"));
case bw(XXXw): // CMPA.w (xxx).w, An
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(d16PC): // CMPA.w (d16, PC), An
case bw(d8PCXn): // CMPA.w (d8, PC, Xn), An
case bw(d16An): // CMPA.w (d16, An), An
case bw(d8AnXn): // CMPA.w (d8, An, Xn), An
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nr", mode), { ea(0) }));
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(Action::PerformOperation, seq("np n"));
break;
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
case l(XXXl): // CMPA.l (xxx).l, An
op(Action::None, seq("np"));
case l(XXXw): // CMPA.l (xxx).w, An
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(d16PC): // CMPA.l (d16, PC), An
case l(d8PCXn): // CMPA.l (d8, PC, Xn), An
case l(d16An): // CMPA.l (d16, An), An
case l(d8AnXn): // CMPA.l (d8, An, Xn), An
Further simplifies CMPA.
2019-04-21 01:23:36 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nR+ nr", mode), { ea(0), ea(0) }));
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(Action::PerformOperation, seq("np n"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Imm): // CMPA.w #, An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
op(Action::PerformOperation, seq("np np n"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Imm): // CMPA.l #, An
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("np np n"));
break;
}
} break;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
case Decoder::CMPI: {
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
if(ea_mode == An) continue;
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const auto destination_mode = ea_mode;
const auto destination_register = ea_register;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
storage_.instructions[instruction].set_destination(storage_, destination_mode, destination_register);
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
const int mode = combined_mode(destination_mode, destination_register);
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
case bw(Dn): // CMPI.bw #, Dn
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation, seq("np np"));
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Dn): // CMPI.l #, Dn
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::None, seq("np"));
op(Action::PerformOperation, seq("np np n"));
break;
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(Ind): // CMPI.bw #, (An)
case bw(PostInc): // CMPI.bw #, (An)+
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { a(destination_register) }, !is_byte_access));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(destination_register) | MicroOp::DestinationMask);
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
}
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(Ind): // CMPI.l #, (An)
case l(PostInc): // CMPI.l #, (An)+
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nRd+ nrd np", { ea(1), ea(1) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::Increment4) | MicroOp::DestinationMask);
}
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(PreDec): // CMPI.bw #, -(An)
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np n"));
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(destination_register) | MicroOp::DestinationMask, seq("nrd np", { a(destination_register) }, !is_byte_access));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(PreDec): // CMPI.l #, -(An)
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("np"));
Adds decoding of ADDA and SUBA.
2019-04-04 02:39:01 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np n"));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(XXXw): // CMPI.bw #, (xxx).w
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(d16An): // CMPI.bw #, (d16, An)
case bw(d8AnXn): // CMPI.bw #, (d8, An, Xn)
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op( address_action_for_mode(mode) | MicroOp::DestinationMask,
Inserts missing program fetch for CMPI.bw #, (d8/16...).
2019-04-24 18:45:24 +00:00
seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(d16An): // CMPI.l #, (d16, An)
case l(d8AnXn): // CMPI.l #, (d8, An, Xn)
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Implements LEA.
2019-03-27 02:07:28 +00:00
op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(XXXw): // CMPI.l #, (xxx).w
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nRd+ nrd np", { ea(1), ea(1) }));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case bw(XXXl): // CMPI.bw #, (xxx).l
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nrd np", { ea(1) }, !is_byte_access));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case l(XXXl): // CMPI.l #, (xxx).l
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::None, seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nRd+ nrd np", { ea(1), ea(1) }));
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
op(Action::PerformOperation);
break;
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
}
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
} break;
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
case Decoder::CMPM: {
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_source(storage_, 1, ea_register);
storage_.instructions[instruction].set_destination(storage_, 1, data_register);
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
const bool is_byte_operation = operation == Operation::CMPb;
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
switch(operation) {
default: continue;
case Operation::CMPb: // CMPM.b, (An)+, (An)+
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
case Operation::CMPw: { // CMPM.w, (An)+, (An)+
op(Action::None, seq("nr nrd np", { a(data_register), a(ea_register) }, !is_byte_operation));
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
op(Action::PerformOperation);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
const int source_inc = inc(ea_register);
const int destination_inc = inc(data_register);
if(destination_inc == source_inc) {
op(destination_inc | MicroOp::SourceMask | MicroOp::DestinationMask);
} else {
op(destination_inc | MicroOp::DestinationMask);
op(source_inc | MicroOp::SourceMask);
}
} break;
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-09 02:40:38 +00:00
case Operation::CMPl:
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask,
seq("nR+ nr nRd+ nrd np", {ea(0), ea(0), ea(1), ea(1)}));
op(Action::PerformOperation);
op(int(Action::Increment4) | MicroOp::SourceMask | MicroOp::DestinationMask);
break;
}
} break;
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. Also corrects the BSR return address.
2019-04-16 23:50:10 +00:00
case Decoder::Scc_DBcc: {
Implements Scc.
2019-04-15 02:39:13 +00:00
if(ea_mode == 1) {
// This is a DBcc. Decode as such.
Corrects decoding of DBcc.
2019-04-15 13:49:23 +00:00
operation = Operation::DBcc;
Implements Scc.
2019-04-15 02:39:13 +00:00
storage_.instructions[instruction].source = &storage_.data_[ea_register];
// Jump straight into deciding what steps to take next,
// which will be selected dynamically.
op(Action::PerformOperation);
op();
} else {
// This is an Scc.
// Scc is inexplicably a read-modify-write operation.
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
case Dn:
op(Action::PerformOperation, seq("np"));
// TODO: if condition true, an extra n.
break;
case Ind:
case PostInc:
op(Action::PerformOperation, seq("nr np nw", { a(ea_register), a(ea_register) }, false));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::DestinationMask);
Implements Scc.
2019-04-15 02:39:13 +00:00
}
break;
case PreDec:
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(ea_register) | MicroOp::DestinationMask);
Implements Scc.
2019-04-15 02:39:13 +00:00
op(Action::PerformOperation, seq("n nr np nw", { a(ea_register), a(ea_register) }, false));
break;
case XXXl:
Corrects Scc and DBcc (xxx).l and (xxx).w.
2019-05-09 10:28:55 +00:00
op(Action::None, seq("np"));
case XXXw:
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case d16An:
case d8AnXn:
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd", mode), { ea(1) } , false));
Implements Scc.
2019-04-15 02:39:13 +00:00
op(Action::PerformOperation, seq("np nw", { ea(1) } , false));
break;
}
}
Implements DBcc.
2019-04-07 03:21:01 +00:00
} break;
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
case Decoder::JSR: {
Attempts to fix register-relative JSRs.
2019-05-09 10:43:07 +00:00
// Ensure a proper source register is connected up for (d16, An) and (d8, An, Xn)-type addressing.
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
// ... but otherwise assume that the true source of a destination will be the computed source address.
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
storage_.instructions[instruction].source = &storage_.effective_address_[0];
Attempts to fix register-relative JSRs.
2019-05-09 10:43:07 +00:00
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
case Ind: // JSR (An)
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask);
Mental delusion lifted: JSR doesn't look enough like BSR.
2019-04-17 14:02:14 +00:00
op(Action::PrepareJSR);
Adjusts JSR behaviour and further extends MOVE.
2019-04-16 02:02:52 +00:00
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case XXXl: // JSR (xxx).L
op(Action::None, seq("np"));
case XXXw: // JSR (xxx).W
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
case d16PC: // JSR (d16, PC)
case d16An: // JSR (d16, An)
Mental delusion lifted: JSR doesn't look enough like BSR.
2019-04-17 14:02:14 +00:00
op(Action::PrepareJSR);
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask);
Corrects a couple of JSR and JMP addressing modes.
2019-04-16 02:37:11 +00:00
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
break;
case d8PCXn: // JSR (d8, PC, Xn)
case d8AnXn: // JSR (d8, An, Xn)
Mental delusion lifted: JSR doesn't look enough like BSR.
2019-04-17 14:02:14 +00:00
op(Action::PrepareJSR);
Corrects a couple of JSR and JMP addressing modes.
2019-04-16 02:37:11 +00:00
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
break;
}
} break;
case Decoder::RTS: {
op(Action::PrepareRTS, seq("nU nu"));
op(Action::PerformOperation, seq("np np"));
} break;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
case Decoder::JMP: {
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
switch(mode) {
default: continue;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case Ind: // JMP (An)
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask);
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
op(Action::PerformOperation, seq("np np"));
break;
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
case XXXw: // JMP (xxx).W
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case d16PC: // JMP (d16, PC)
case d16An: // JMP (d16, An)
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask);
Corrects a couple of JSR and JMP addressing modes.
2019-04-16 02:37:11 +00:00
op(Action::PerformOperation, seq("n np np"));
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case d8PCXn: // JMP (d8, PC, Xn)
case d8AnXn: // JMP (d8, An, Xn)
Corrects a couple of JSR and JMP addressing modes.
2019-04-16 02:37:11 +00:00
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n nn np np"));
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
break;
Fixes register-relative JMP and JSR.
2019-06-03 19:29:50 +00:00
case XXXl: // JMP (xxx).L
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
op(Action::None, seq("np"));
Takes a run at JSR and RTS.
2019-04-15 19:14:38 +00:00
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("np np"));
break;
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
}
} break;
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
case Decoder::PEA: {
Further fixes PEA, and OR/AND/EOR Dn, (An).
2019-05-29 18:37:15 +00:00
storage_.instructions[instruction].set_source(storage_, An, ea_register);
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
storage_.instructions[instruction].destination_address = &storage_.address_[7];
// Common to all modes: decrement A7.
op(int(Action::Decrement4) | MicroOp::DestinationMask);
Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter.
2019-05-06 02:47:54 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
switch(mode) {
default: continue;
case Ind: // PEA (An)
Further fixes PEA, and OR/AND/EOR Dn, (An).
2019-05-29 18:37:15 +00:00
operation = Operation::MOVEAl;
Implements PEA. This decreases the unimplemented count by 28 from 11841 to 11813.
2019-04-26 17:49:59 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
op(Action::PerformOperation, seq("np nW+ nw", { ea(1), ea(1) }));
break;
case XXXl: // PEA (XXX).l
case XXXw: // PEA (XXX).w
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
break;
case d16An: // PEA (d16, An)
case d16PC: // PEA (d16, PC)
case d8AnXn: // PEA (d8, An, Xn)
case d8PCXn: // PEA (d8, PC, Xn)
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));
break;
}
} break;
Implements LEA.
2019-03-27 02:07:28 +00:00
case Decoder::LEA: {
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_destination(storage_, An, data_register);
Implements LEA.
2019-03-27 02:07:28 +00:00
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Completes conversion away from magic constants.
2019-04-12 19:48:29 +00:00
storage_.instructions[instruction].source_address = &storage_.address_[ea_register];
storage_.instructions[instruction].source =
(mode == Ind) ?
&storage_.address_[ea_register] :
&storage_.effective_address_[0];
Implements LEA.
2019-03-27 02:07:28 +00:00
switch(mode) {
default: continue;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case Ind: // LEA (An), An (i.e. MOVEA)
Implements LEA.
2019-03-27 02:07:28 +00:00
op(Action::PerformOperation, seq("np"));
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case XXXl: // LEA (xxx).L, An
op(Action::None, seq("np"));
case XXXw: // LEA (xxx).W, An
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case d16An: // LEA (d16, An), An
Completes conversion away from magic constants.
2019-04-12 19:48:29 +00:00
case d16PC: // LEA (d16, PC), An
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq("np np"));
Implements LEA.
2019-03-27 02:07:28 +00:00
op(Action::PerformOperation);
break;
Completes conversion away from magic constants.
2019-04-12 19:48:29 +00:00
case d8AnXn: // LEA (d8, An, Xn), An
case d8PCXn: // LEA (d8, PC, Xn), An
Implements LEA.
2019-03-27 02:07:28 +00:00
op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np n np"));
op(Action::PerformOperation);
break;
}
} break;
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
case Decoder::MOVEfromSR_NBCD: {
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
is_byte_access = operation == Operation::NBCD;
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
case Dn: // MOVE SR, Dn
op(Action::PerformOperation, seq("np n"));
break;
case Ind: // MOVE SR, (An)
case PostInc: // MOVE SR, (An)+
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
if(mode == PostInc) {
op(int(Action::Increment2) | MicroOp::DestinationMask);
}
break;
case PreDec: // MOVE SR, -(An)
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
op(int(Action::Decrement2) | MicroOp::DestinationMask, seq("n nrd", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
break;
case XXXl: // MOVE SR, (xxx).l
op(Action::None, seq("np"));
case XXXw: // MOVE SR, (xxx).w
case d16An: // MOVE SR, (d16, An)
case d8AnXn: // MOVE SR, (d8, An, Xn)
Implements NBCD. Now outstanding: 1891.
2019-04-28 01:29:50 +00:00
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd", mode), { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { ea(1) }, !is_byte_access));
Implements MOVE from SR.
2019-04-25 18:39:32 +00:00
break;
}
} break;
Implements MOVE to CCR.
2019-04-08 02:24:17 +00:00
case Decoder::MOVEtoSRCCR: {
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
if(ea_mode == An) continue;
Implements CMP.
2019-04-06 14:41:19 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Implements MOVE to CCR.
2019-04-08 02:24:17 +00:00
storage_.instructions[instruction].requires_supervisor = (operation == Operation::MOVEtoSR);
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
/* DEVIATION FROM YACHT.TXT: it has all of these reading an extra word from the PC;
this looks like a mistake so I've padded with nil cycles in the middle. */
Implements CMP.
2019-04-06 14:41:19 +00:00
const int mode = combined_mode(ea_mode, ea_register);
Takes a run at CMPI. Also factors out a couple of mode things, clarifies on where things from the prefetch are assembled to, and switches to ordering implemented instructions alphabetically.
2019-03-25 03:05:57 +00:00
switch(mode) {
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
default: continue;
case Dn: // MOVE Dn, SR
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
op(Action::PerformOperation, seq("nn np"));
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case Ind: // MOVE (An), SR
case PostInc: // MOVE (An)+, SR
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::None, seq("nr nn nn np", { a(ea_register) }));
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
if(mode == PostInc) {
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
op(int(Action::Increment2) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case PreDec: // MOVE -(An), SR
Implements CMP.
2019-04-06 14:41:19 +00:00
op(Action::Decrement2, seq("n nr nn nn np", { a(ea_register) }));
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
op(Action::PerformOperation);
break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case XXXl: // MOVE (xxx).L, SR
op(Action::None, seq("np"));
case XXXw: // MOVE (xxx).W, SR
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case d16PC: // MOVE (d16, PC), SR
case d8PCXn: // MOVE (d8, PC, Xn), SR
case d16An: // MOVE (d16, An), SR
case d8AnXn: // MOVE (d8, An, Xn), SR
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nr nn nn np", mode), { ea(0) }));
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
op(Action::PerformOperation);
break;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
case Imm: // MOVE #, SR
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
op(int(Action::PerformOperation), seq("np nn nn np"));
break;
}
} break;
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
case Decoder::MOVEq: {
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].destination = &storage_.data_[data_register];
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
op(Action::PerformOperation, seq("np"));
} break;
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
case Decoder::MOVEP: {
storage_.instructions[instruction].set_destination(storage_, An, ea_register);
storage_.instructions[instruction].set_source(storage_, Dn, data_register);
switch(operation) {
default: continue;
// Both of the MOVEP to memory instructions perform their operation first — it will
// break up the source value into 8-bit chunks for the write section.
case Operation::MOVEPtoMw:
op(Action::PerformOperation);
op(int(Action::CalcD16An) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }, false));
break;
case Operation::MOVEPtoMl:
op(Action::PerformOperation);
op(int(Action::CalcD16An) | MicroOp::DestinationMask, seq("np nW+ nWr+ nw+ nwr np", { ea(1), ea(1), ea(1), ea(1) }, false));
break;
case Operation::MOVEPtoRw:
op(int(Action::CalcD16An) | MicroOp::DestinationMask, seq("np nRd+ nrd np", { ea(1), ea(1) }, false));
op(Action::PerformOperation);
break;
case Operation::MOVEPtoRl:
op(int(Action::CalcD16An) | MicroOp::DestinationMask, seq("np nRd+ nR+ nrd+ nr np", { ea(1), ea(1), ea(1), ea(1) }, false));
op(Action::PerformOperation);
break;
}
} break;
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
case Decoder::MOVEM: {
// For the sake of commonality, both to R and to M will evaluate their addresses
// as if they were destinations.
storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
// Standard prefix: acquire the register selection flags and fetch the next program
// word to replace them.
op(Action::CopyNextWord, seq("np"));
// Do whatever is necessary to calculate the proper start address.
const int mode = combined_mode(ea_mode, ea_register);
const bool is_to_m = (operation == Operation::MOVEMtoMl || operation == Operation::MOVEMtoMw);
switch(mode) {
default: continue;
case Ind:
case PreDec:
case PostInc: {
// Deal with the illegal combinations.
if(mode == PostInc && is_to_m) continue;
if(mode == PreDec && !is_to_m) continue;
} break;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case XXXl:
op(Action::None, seq("np"));
case XXXw:
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
case d16An:
case d8AnXn:
case d16PC:
case d8PCXn:
// PC-relative addressing is permitted for moving to registers only.
if((mode == d16PC || mode == d8PCXn) && is_to_m) continue;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np", mode)));
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
break;
}
// Standard suffix: perform the MOVEM, which will mean evaluating the
// register selection flags and substituting the necessary reads or writes.
op(Action::PerformOperation);
// A final program fetch will cue up the next instruction.
Implements MOVEM to R.
2019-04-15 00:02:18 +00:00
op(is_to_m ? Action::MOVEMtoMComplete : Action::MOVEMtoRComplete, seq("np"));
Commits at least to decoding MOVEM.
2019-04-14 18:09:28 +00:00
} break;
Implements MOVE to/from USP.
2019-04-17 20:58:59 +00:00
case Decoder::MOVEUSP: {
storage_.instructions[instruction].requires_supervisor = true;
// Observation here: because this is a privileged instruction, the user stack pointer
Corrects direction of MOVE [to/from] USP.
2019-04-20 02:41:06 +00:00
// definitely isn't currently [copied into] A7.
Implements MOVE to/from USP.
2019-04-17 20:58:59 +00:00
if(instruction & 0x8) {
// Transfer FROM the USP.
storage_.instructions[instruction].source = &storage_.stack_pointers_[0];
storage_.instructions[instruction].set_destination(storage_, An, ea_register);
Corrects direction of MOVE [to/from] USP.
2019-04-20 02:41:06 +00:00
} else {
// Transfer TO the USP.
storage_.instructions[instruction].set_source(storage_, An, ea_register);
storage_.instructions[instruction].destination = &storage_.stack_pointers_[0];
Implements MOVE to/from USP.
2019-04-17 20:58:59 +00:00
}
op(Action::PerformOperation, seq("np"));
} break;
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 22:20:54 +00:00
// Decodes the format used by most MOVEs and all MOVEAs.
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
case Decoder::MOVE: {
Implements all `MOVE Dn, Dn`.
2019-03-17 03:14:18 +00:00
const int destination_mode = (instruction >> 6) & 7;
Commits further to elimination of magic constants.
2019-04-12 17:45:28 +00:00
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
storage_.instructions[instruction].set_destination(storage_, destination_mode, data_register);
Implements all `MOVE Dn, Dn`.
2019-03-17 03:14:18 +00:00
Attempts to unify type decoding a little further.
2019-04-19 17:29:20 +00:00
// These don't come from the usual place.
is_byte_access = mapping.operation == Operation::MOVEb;
is_long_word_access = mapping.operation == Operation::MOVEl;
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
Corrects MOVEA, adds extra test safeguards.
2019-04-12 20:10:17 +00:00
// If the move is to an address register, switch the MOVE to a MOVEA.
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
// Also: there are no byte moves to address registers.
if(destination_mode == An) {
if(is_byte_access) {
continue;
}
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
operation = is_long_word_access ? Operation::MOVEAl : Operation::MOVEAw;
}
Corrects test and resolves all instances of opcodes that are valid but shouldn't be. The converse case will require implementation of the remaining instructions.
2019-04-26 02:54:58 +00:00
// ... there are also no byte moves from address registers.
if(ea_mode == An && is_byte_access) continue;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
// Perform the MOVE[A]'s fetch..
const int combined_source_mode = combined_mode(ea_mode, ea_register, true);
switch(is_long_word_access ? l(combined_source_mode) : bw(combined_source_mode)) {
default: continue;
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(Dn): // MOVE[A].l [An/Dn], <ea>
case bw(Dn): // MOVE[A].bw [An/Dn], <ea>
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(PreDec): // MOVE[A].bw -(An), <ea>
op(dec(ea_register) | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(Ind): // MOVE[A].bw (An), <ea>
case bw(PostInc): // MOVE[A].bw (An)+, <ea>
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
if(combined_source_mode == PostInc) {
op(inc(ea_register) | MicroOp::SourceMask);
}
Implements a few additional MOVEs.
2019-03-28 01:26:04 +00:00
break;
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(PreDec): // MOVE[A].l -(An), <ea>
op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
case l(Ind): // MOVE[A].l (An), <ea>
case l(PostInc): // MOVE[A].l (An)+, <ea>
op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
seq("nR+ nr", { ea(0), ea(0) }));
if(combined_source_mode == PostInc) {
op(inc(ea_register) | MicroOp::SourceMask);
}
Implements a few additional MOVEs.
2019-03-28 01:26:04 +00:00
break;
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(XXXl): // MOVE[A].bw (xxx).L, <ea>
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
op(Action::None, seq("np"));
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(XXXw): // MOVE[A].bw (xxx).W, <ea>
case bw(d16An): // MOVE[A].bw (d16, An), <ea>
case bw(d8AnXn): // MOVE[A].bw (d8, An, Xn), <ea>
case bw(d16PC): // MOVE[A].bw (d16, PC), <ea>
case bw(d8PCXn): // MOVE[A].bw (d8, PC, Xn), <ea>
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
op( address_action_for_mode(combined_source_mode) | MicroOp::SourceMask,
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
seq(pseq("np nr", combined_source_mode), { ea(0) },
!is_byte_access));
Implements a few additional MOVEs.
2019-03-28 01:26:04 +00:00
break;
Starts to make incursions into MOVE[A].l.
2019-03-24 01:03:52 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(XXXl): // MOVE[A].l (xxx).L, <ea>
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
op(Action::None, seq("np"));
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(XXXw): // MOVE[A].l (xxx).W, <ea>
case l(d16An): // MOVE[A].l (d16, An), <ea>
case l(d8AnXn): // MOVE[A].l (d8, An, Xn), <ea>
case l(d16PC): // MOVE[A].l (d16, PC), <ea>
case l(d8PCXn): // MOVE[A].l (d8, PC, Xn), <ea>
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
op( address_action_for_mode(combined_source_mode) | MicroOp::SourceMask,
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
seq(pseq("np nR+ nr", combined_source_mode), { ea(0), ea(0) }));
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(Imm): // MOVE[A].l #, <ea>
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
op(Action::None, seq("np"));
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(Imm): // MOVE[A].bw #, <ea>
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
}
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
// Perform the MOVE[A].
op(Action::PerformOperation);
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
// Perform the MOVE[A]'s store.
const int combined_destination_mode = combined_mode(destination_mode, data_register, true);
switch(is_long_word_access ? l(combined_destination_mode) : bw(combined_destination_mode)) {
default: continue;
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(Dn): // MOVE[A].l <ea>, [An/Dn]
case bw(Dn): // MOVE[A].bw <ea>, [An/Dn]
op(Action::None, seq("np"));
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(PreDec): // MOVE[A].bw <ea>, -(An)
Attempts an implementation of ADDX and SUBX. Leaving 2005 non-[A/F]-line instructions.
2019-04-27 20:57:21 +00:00
op( dec(data_register) | MicroOp::DestinationMask,
seq("np nw", { a(data_register) }, !is_byte_access));
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(Ind): // MOVE[A].bw <ea>, (An)
case bw(PostInc): // MOVE[A].bw <ea>, (An)+
op(Action::None, seq("nw np", { a(data_register) }, !is_byte_access));
if(combined_destination_mode == PostInc) {
op(inc(data_register) | MicroOp::DestinationMask);
}
Attempts to fill in the rest of MOVE x, -(An).
2019-04-18 03:05:16 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(PreDec): // MOVE[A].l <ea>, -(An)
Attempts to fill in the rest of MOVE x, -(An).
2019-04-18 03:05:16 +00:00
op(int(Action::Decrement2) | MicroOp::DestinationMask);
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask,
seq("np nw- nW", { ea(1), ea(1) }));
Attempts to fill in the rest of MOVE x, -(An).
2019-04-18 03:05:16 +00:00
op(int(Action::Decrement2) | MicroOp::DestinationMask);
break;
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(Ind): // MOVE[A].l <ea>, (An)
case l(PostInc): // MOVE[A].l <ea>, (An)+
op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask,
seq("nW+ nw np", { ea(1), ea(1) }));
if(combined_destination_mode == PostInc) {
op(inc(data_register) | MicroOp::DestinationMask);
}
Fixes a bunch of (d16, An)-type MOVEs and implements MOVE (XXX).wl, (d16,An)/etc.
2019-04-17 20:13:35 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(XXXw): // MOVE[A].bw <ea>, (xxx).W
case bw(d16An): // MOVE[A].bw <ea>, (d16, An)
case bw(d8AnXn): // MOVE[A].bw <ea>, (d8, An, Xn)
op( address_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask,
seq(pseq("np nw np", combined_destination_mode), { ea(1) },
!is_byte_access));
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(XXXw): // MOVE[A].l <ea>, (xxx).W
case l(d16An): // MOVE[A].l <ea>, (d16, An)
case l(d8AnXn): // MOVE[A].l <ea>, (d8, An, Xn)
op( address_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask,
seq(pseq("np nW+ nw np", combined_destination_mode), { ea(1), ea(1) }));
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
break;
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case bw(XXXl): // MOVE[A].bw <ea>, (xxx).L
Completes conversion away from magic constants.
2019-04-12 19:48:29 +00:00
op(Action::None, seq("np"));
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
switch(combined_source_mode) { // The pattern here is a function of source and destination.
case Dn:
case Imm:
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nw np", { ea(1) }, !is_byte_access));
break;
default:
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("nw np np", { ea(1) }, !is_byte_access));
break;
}
Implements further MOVEs and fixes a potential error in program formation.
2019-04-01 02:34:28 +00:00
break;
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
case l(XXXl): // MOVE[A].l <ea>, (xxx).L
Fleshes out MOVE, (XXX) a little further.
2019-04-12 21:16:03 +00:00
op(Action::None, seq("np"));
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
switch(combined_source_mode) { // The pattern here is a function of source and destination.
case Dn:
case Imm:
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nW+ nw np", { ea(1), ea(1) }));
break;
default:
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("nW+ nw np np", { ea(1), ea(1) }));
break;
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
}
Simplifies and corrects MOVE logic.
2019-05-28 19:17:03 +00:00
break;
Begins a cleanup procedure on MOVE.
2019-04-19 03:25:19 +00:00
}
Implements all `MOVE Dn, Dn`.
2019-03-17 03:14:18 +00:00
} break;
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
case Decoder::RESET:
Corrects CMPI and documentation; implements JMP.
2019-04-01 01:13:26 +00:00
storage_.instructions[instruction].requires_supervisor = true;
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-30 03:40:54 +00:00
op(Action::None, seq("nn _ np"));
break;
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
case Decoder::TRAP: {
// TRAP involves some oddly-sequenced stack writes, so is calculated
// at runtime; also the same sequence is used for illegal instructions.
// So the entirety is scheduled at runtime.
op(Action::PerformOperation);
op();
} break;
Takes a run at TRAPV. ... to leave 1466 as the unimplemented count.
2019-04-28 19:52:58 +00:00
case Decoder::TRAPV: {
op(Action::None, seq("np"));
op(Action::PerformOperation);
op();
} break;
Attempts an implementation of CHK. 1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 19:47:21 +00:00
case Decoder::CHK: {
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
switch(mode) {
default: continue;
case Dn: // CHK Dn, Dn
op(Action::None, seq("np"));
break;
case Ind: // CHK (An), Dn
case PostInc: // CHK (An)+, Dn
op(Action::None, seq("nr np", { a(ea_register) }));
if(mode == PostInc) {
op(int(Action::Increment2) | MicroOp::SourceMask);
}
break;
case PreDec: // CHK (An)-, Dn
op(int(Action::Decrement2) | MicroOp::SourceMask, seq("n nr np", { a(ea_register) }));
break;
case XXXl: // CHK (xxx).l, Dn
op(Action::None, seq("np"));
case XXXw: // CHK (xxx).w, Dn
case d16An: // CHK (d16, An), Dn
case d16PC: // CHK (d16, PC), Dn
case d8AnXn: // CHK (d8, An, Xn), Dn
case d8PCXn: // CHK (d8, PC, Xn), Dn
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nr", mode), { ea(0) }));
break;
case Imm: // CHK #, Dn
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
break;
}
// The nn n here is correct if no exception is issued; otherwise this sequence will
// be replaced.
op(Action::PerformOperation, seq("nn n"));
} break;
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
case Decoder::TST: {
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
Completes TST.
2019-04-15 20:28:20 +00:00
case bw(Dn): // TST.bw Dn
case l(Dn): // TST.l Dn
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
op(Action::PerformOperation, seq("np"));
break;
Completes TST.
2019-04-15 20:28:20 +00:00
case bw(PreDec): // TST.bw -(An)
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(dec(ea_register) | MicroOp::SourceMask, seq("n"));
Completes TST.
2019-04-15 20:28:20 +00:00
case bw(Ind): // TST.bw (An)
case bw(PostInc): // TST.bw (An)+
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np"));
if(mode == PostInc) {
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
op(inc(ea_register) | MicroOp::SourceMask);
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
}
break;
Completes TST.
2019-04-15 20:28:20 +00:00
case l(PreDec): // TST.l -(An)
Adds predecrement TSTs, increases QL running time, reduces logging.
2019-04-15 16:36:08 +00:00
op(int(Action::Decrement4) | MicroOp::SourceMask, seq("n"));
Completes TST.
2019-04-15 20:28:20 +00:00
case l(Ind): // TST.l (An)
case l(PostInc): // TST.l (An)+
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq("np"));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::SourceMask);
}
break;
Completes TST.
2019-04-15 20:28:20 +00:00
case bw(XXXl): // TST.bw (xxx).l
op(Action::None, seq("np"));
case bw(XXXw): // TST.bw (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case bw(d16An): // TST.bw (d16, An)
case bw(d8AnXn): // TST.bw (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nr", mode), { ea(0) }, !is_byte_access));
Completes TST.
2019-04-15 20:28:20 +00:00
op(Action::PerformOperation, seq("np"));
break;
case l(XXXl): // TST.l (xxx).l
op(Action::None, seq("np"));
case l(XXXw): // TST.l (xxx).w
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
case l(d16An): // TST.l (d16, An)
case l(d8AnXn): // TST.l (d8, An, Xn)
op(address_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np nR+ nr", mode), { ea(0), ea(0) }));
Completes TST.
2019-04-15 20:28:20 +00:00
op(Action::PerformOperation, seq("np"));
break;
Implements the first few addressing modes for TST.
2019-04-15 14:03:52 +00:00
}
} break;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
default:
std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
Attempts properly to honour the bus-op and microcycle contract.
2019-03-17 02:36:09 +00:00
continue;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
// Add a terminating micro operation if necessary.
if(!storage_.all_micro_ops_.back().is_terminal()) {
storage_.all_micro_ops_.emplace_back();
}
Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter.
2019-05-06 02:47:54 +00:00
// Ensure that steps that weren't meant to look terminal aren't terminal; also check
// for improperly encoded address calculation-type actions.
Implements further MOVEs and fixes a potential error in program formation.
2019-04-01 02:34:28 +00:00
for(auto index = micro_op_start; index < storage_.all_micro_ops_.size() - 1; ++index) {
Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter.
2019-05-06 02:47:54 +00:00
// All of the actions below must also nominate a source and/or destination.
switch(storage_.all_micro_ops_[index].action) {
default: break;
case int(Action::CalcD16PC):
case int(Action::CalcD8PCXn):
case int(Action::CalcD16An):
case int(Action::CalcD8AnXn):
case int(Action::AssembleWordAddressFromPrefetch):
case int(Action::AssembleLongWordAddressFromPrefetch):
case int(Action::CopyToEffectiveAddress):
assert(false);
}
Implements further MOVEs and fixes a potential error in program formation.
2019-04-01 02:34:28 +00:00
if(storage_.all_micro_ops_[index].is_terminal()) {
storage_.all_micro_ops_[index].bus_program = seq("");
}
}
Attempts properly to honour the bus-op and microcycle contract.
2019-03-17 02:36:09 +00:00
// Install the operation and make a note of where micro-ops begin.
Implements MOVEA as distinct from MOVE. At least as far as MOVE is implemented, that is.
2019-03-22 23:25:53 +00:00
storage_.instructions[instruction].operation = operation;
Joins some commonalities, shaving about 150 lines of code.
2019-04-30 02:37:23 +00:00
micro_op_pointers[size_t(instruction)] = size_t(micro_op_start);
Attempts properly to honour the bus-op and microcycle contract.
2019-03-17 02:36:09 +00:00
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
// Don't search further through the list of possibilities, unless this is a debugging build,
// in which case verify there are no double mappings.
#ifndef NDEBUG
++hits;
assert(hits == 1);
#else
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
break;
Implements AND, OR and EOR. As well as introducing a little more nuance to the double-decoding test.
2019-04-18 20:34:48 +00:00
#endif
Embraces a more communicative 68000 bus.
2019-03-10 21:27:34 +00:00
}
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Corrects byte increment/decrement actions for A7.
2019-04-24 17:01:08 +00:00
#undef inc
#undef dec
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
// Throw in the interrupt program.
const auto interrupt_pointer = storage_.all_micro_ops_.size();
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
// WORKAROUND FOR THE BE68000 MAIN LOOP. Hopefully temporary.
op(Action::None, seq(""));
// Perform a single write and then a cycle that will obtain an interrupt vector, or else dictate an autovector or a spurious interrupt.
Takes a shot at the synchronous bus.
2019-05-03 18:20:59 +00:00
op(Action::PrepareINT, seq("n nn nw int", { &storage_.precomputed_addresses_[0] }));
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
// The reset of the standard trap steps occur here; PrepareINT will set them up according to the vector received.
Takes a shot at the synchronous bus.
2019-05-03 18:20:59 +00:00
op(Action::PrepareINTVector, seq("nn n nw nW nV nv np np", { &storage_.precomputed_addresses_[1], &storage_.precomputed_addresses_[2] }));
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
// Terminate the sequence.
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
op();
Begins rooting out magic constants.
2019-04-12 02:31:17 +00:00
#undef Dn
#undef An
#undef Ind
#undef PostDec
#undef PreDec
#undef d16An
#undef d8AnXn
#undef XXXw
#undef XXXl
#undef d16PC
#undef d8PCXn
#undef Imm
#undef bw
#undef l
#undef source_dest
Reuse of addresses is also no longer implicit.
2019-04-04 01:27:11 +00:00
#undef ea
#undef a
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
#undef seq
#undef op
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-30 03:13:41 +00:00
#undef pseq
Makes a further push into the MOVEs. With some quick notation shortening.
2019-03-21 03:21:02 +00:00
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
/*!
Iterates through the micro-sequence beginning at @c start, finalising bus_program
pointers that have been transiently stored as relative to @c arbitrary_base.
*/
const auto link_operations = [this](MicroOp *start, BusStep *arbitrary_base) {
while(!start->is_terminal()) {
const auto offset = size_t(start->bus_program - arbitrary_base);
assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
start->bus_program = &storage_.all_bus_steps_[offset];
++start;
}
};
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
// Finalise micro-op and program pointers.
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
for(size_t instruction = 0; instruction < 65536; ++instruction) {
if(micro_op_pointers[instruction] != std::numeric_limits<size_t>::max()) {
storage_.instructions[instruction].micro_operations = &storage_.all_micro_ops_[micro_op_pointers[instruction]];
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
link_operations(storage_.instructions[instruction].micro_operations, &arbitrary_base);
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
}
Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
}
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
Takes further steps towards supporting interrupts. Specifically: * introduces the necessary bus signalling; and * adds corresponding functional steps. Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 19:19:24 +00:00
// Link up the interrupt micro ops.
storage_.interrupt_micro_ops_ = &storage_.all_micro_ops_[interrupt_pointer];
link_operations(storage_.interrupt_micro_ops_, &arbitrary_base);
Ensures `replace_write_values` works in release builds.
2019-05-29 23:00:53 +00:00
std::cout << storage_.all_bus_steps_.size() << " total steps" << std::endl;
Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
}
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
private:
ProcessorStorage &storage_;
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
Reduces conversions to vector.
2019-05-30 16:08:35 +00:00
std::initializer_list<RegisterPair16 *>::const_iterator replace_write_values(BusStep *start, std::initializer_list<RegisterPair16 *>::const_iterator value) {
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
while(!start->is_terminal()) {
// Look for any bus step that writes. Then replace its value, and that of the cycle before it.
if(start->microcycle.data_select_active() && !(start->microcycle.operation & Microcycle::Read) && !(start->microcycle.operation & Microcycle::InterruptAcknowledge)) {
start[0].microcycle.value = start[-1].microcycle.value = *value;
++value;
}
++start;
}
return value;
}
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
/* struct BusStepOrderer {
bool operator()( BusStep const& lhs, BusStep const& rhs ) const {
int action_diff = int(lhs.action) - int(rhs.action);
if(action_diff < 0) {
return true;
}
if(action_diff > 0) {
return false;
}
return
std::make_tuple(lhs.microcycle.value, lhs.microcycle.address, lhs.microcycle.length, lhs.microcycle.operation) <
std::make_tuple(rhs.microcycle.value, rhs.microcycle.address, rhs.microcycle.length, rhs.microcycle.operation);
}
};
std::map<BusStep, std::vector<size_t>, BusStepOrderer> locations_by_bus_step_;*/
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
};
Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-13 02:46:31 +00:00
}
Begins some very early sketching out of a 68000.
2019-03-09 05:00:23 +00:00
}
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-12 02:47:58 +00:00
Implements MOVEP. 371 is now the alleged number of missing opcodes. But I'd dare imagine it's more like three or four.
2019-04-29 02:52:54 +00:00
CPU::MC68000::ProcessorStorage::ProcessorStorage() {
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
ProcessorStorageConstructor constructor(*this);
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-13 02:46:31 +00:00
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
// Create the special programs.
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-18 01:57:00 +00:00
const size_t reset_offset = constructor.assemble_program("n n n n n nn nF nf nV nv np np");
Implements DBcc.
2019-04-07 03:21:01 +00:00
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
const size_t branch_taken_offset = constructor.assemble_program("n np np");
const size_t branch_byte_not_taken_offset = constructor.assemble_program("nn np");
const size_t branch_word_not_taken_offset = constructor.assemble_program("nn np np");
Implements (arguably: fixes) BSR.
2019-04-16 03:20:36 +00:00
const size_t bsr_offset = constructor.assemble_program("np np");
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-13 02:46:31 +00:00
Implements DBcc.
2019-04-07 03:21:01 +00:00
const size_t dbcc_condition_true_offset = constructor.assemble_program("nn np np");
const size_t dbcc_condition_false_no_branch_offset = constructor.assemble_program("n nr np np", { &dbcc_false_address_ });
const size_t dbcc_condition_false_branch_offset = constructor.assemble_program("n np np");
Ensures DBcc properly signals program fetches.
2019-04-22 02:54:20 +00:00
// That nr in dbcc_condition_false_no_branch_offset is to look like an np from the wrong address.
Implements DBcc.
2019-04-07 03:21:01 +00:00
Implements MOVEM to R.
2019-04-15 00:02:18 +00:00
// The reads steps needs to be 32 long-word reads plus an overflow word; the writes just the long words.
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 18:31:13 +00:00
// Addresses and data sources/targets will be filled in at runtime, so anything will do here.
std::string movem_reads_pattern, movem_writes_pattern;
std::vector<uint32_t *> addresses;
Implements MOVEM to R.
2019-04-15 00:02:18 +00:00
for(auto c = 0; c < 64; ++c) {
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 18:31:13 +00:00
movem_reads_pattern += "nr ";
Implements MOVEM to R.
2019-04-15 00:02:18 +00:00
movem_writes_pattern += "nw ";
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 18:31:13 +00:00
addresses.push_back(nullptr);
}
Implements MOVEM to R.
2019-04-15 00:02:18 +00:00
movem_reads_pattern += "nr";
addresses.push_back(nullptr);
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
const size_t movem_read_offset = constructor.assemble_program(movem_reads_pattern, addresses);
const size_t movem_write_offset = constructor.assemble_program(movem_writes_pattern, addresses);
// Target addresses and values will be filled in by TRAP/illegal too.
Attempts an implementation of CHK. 1467 is now the official count of things to implement, though I'm starting to get suspicious.
2019-04-28 19:47:21 +00:00
const size_t trap_offset = constructor.assemble_program("r nw nw nW nV nv np np", { &precomputed_addresses_[0], &precomputed_addresses_[1], &precomputed_addresses_[2] });
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
const size_t bus_error_offset =
constructor.assemble_program(
"nn nw nw nW nw nw nw nW nV nv np np",
{
&precomputed_addresses_[0],
&precomputed_addresses_[1],
&precomputed_addresses_[2],
&precomputed_addresses_[3],
&precomputed_addresses_[4],
&precomputed_addresses_[5],
&precomputed_addresses_[6]
}
);
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 18:31:13 +00:00
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 20:11:01 +00:00
// Chuck in the proper micro-ops for handling an exception.
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
const auto short_exception_offset = all_micro_ops_.size();
all_micro_ops_.emplace_back(ProcessorBase::MicroOp::Action::None);
all_micro_ops_.emplace_back();
const auto long_exception_offset = all_micro_ops_.size();
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 20:11:01 +00:00
all_micro_ops_.emplace_back(ProcessorBase::MicroOp::Action::None);
all_micro_ops_.emplace_back();
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
// Install operations.
Adds further missing includes.
2019-05-03 18:42:36 +00:00
#ifndef NDEBUG
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
const std::clock_t start = std::clock();
Adds further missing includes.
2019-05-03 18:42:36 +00:00
#endif
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-17 01:47:46 +00:00
constructor.install_instructions();
Adds further missing includes.
2019-05-03 18:42:36 +00:00
#ifndef NDEBUG
Takes a run at divide-by-zero exceptions and starts looking towards ways to improve startup time.
2019-04-30 02:08:16 +00:00
std::cout << "Construction took " << double(std::clock() - start) / double(CLOCKS_PER_SEC / 1000) << "ms" << std::endl;
Adds further missing includes.
2019-05-03 18:42:36 +00:00
#endif
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-13 02:46:31 +00:00
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
// Realise the special programs as direct pointers.
reset_bus_steps_ = &all_bus_steps_[reset_offset];
Implements DBcc.
2019-04-07 03:21:01 +00:00
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
branch_taken_bus_steps_ = &all_bus_steps_[branch_taken_offset];
branch_byte_not_taken_bus_steps_ = &all_bus_steps_[branch_byte_not_taken_offset];
branch_word_not_taken_bus_steps_ = &all_bus_steps_[branch_word_not_taken_offset];
Implements (arguably: fixes) BSR.
2019-04-16 03:20:36 +00:00
bsr_bus_steps_ = &all_bus_steps_[bsr_offset];
I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs.
2019-03-14 01:08:13 +00:00
Implements DBcc.
2019-04-07 03:21:01 +00:00
dbcc_condition_true_steps_ = &all_bus_steps_[dbcc_condition_true_offset];
dbcc_condition_false_no_branch_steps_ = &all_bus_steps_[dbcc_condition_false_no_branch_offset];
Ensures DBcc properly signals program fetches.
2019-04-22 02:54:20 +00:00
dbcc_condition_false_no_branch_steps_[1].microcycle.operation |= Microcycle::IsProgram;
dbcc_condition_false_no_branch_steps_[2].microcycle.operation |= Microcycle::IsProgram;
Implements DBcc.
2019-04-07 03:21:01 +00:00
dbcc_condition_false_branch_steps_ = &all_bus_steps_[dbcc_condition_false_branch_offset];
Takes a run at TRAP.
2019-04-18 02:21:56 +00:00
movem_read_steps_ = &all_bus_steps_[movem_read_offset];
movem_write_steps_ = &all_bus_steps_[movem_write_offset];
// Link the trap steps but also fill in the program counter as the source
// for its parts, and use the computed addresses.
//
// Order of output is: PC.l, SR, PC.h.
trap_steps_ = &all_bus_steps_[trap_offset];
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
constructor.replace_write_values(trap_steps_, { &program_counter_.halves.low, &destination_bus_data_[0].halves.low, &program_counter_.halves.high });
// Fill in the same order of writes for the interrupt micro-ops, though it divides the work differently.
constructor.replace_write_values(interrupt_micro_ops_, { &program_counter_.halves.low, &destination_bus_data_[0].halves.low, &program_counter_.halves.high });
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 18:31:13 +00:00
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
// Link the bus error exception steps and fill in the proper sources.
bus_error_steps_ = &all_bus_steps_[bus_error_offset];
Alters the order of interrupt bus activity, to bring it into line with a real 68000.
2019-05-02 19:25:43 +00:00
constructor.replace_write_values(bus_error_steps_, {
&program_counter_.halves.low,
&destination_bus_data_[0].halves.low,
&program_counter_.halves.high,
&decoded_instruction_,
&effective_address_[0].halves.low,
&destination_bus_data_[0].halves.high,
&effective_address_[0].halves.high
});
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
Makes an attempt at RTE and RTR.
2019-04-19 00:50:58 +00:00
// Also relink the RTE and RTR bus steps to collect the program counter.
//
// Assumed order of input: PC.h, SR, PC.l (i.e. the opposite of TRAP's output).
for(const int instruction: { 0x4e73, 0x4e77 }) {
auto steps = instructions[instruction].micro_operations[0].bus_program;
steps[0].microcycle.value = steps[1].microcycle.value = &program_counter_.halves.high;
steps[4].microcycle.value = steps[5].microcycle.value = &program_counter_.halves.low;
}
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
// Setup the stop cycle.
stop_cycle_.length = HalfCycles(2);
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 20:11:01 +00:00
// Complete linkage of the exception micro program.
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 23:24:22 +00:00
short_exception_micro_ops_ = &all_micro_ops_[short_exception_offset];
short_exception_micro_ops_->bus_program = trap_steps_;
long_exception_micro_ops_ = &all_micro_ops_[long_exception_offset];
long_exception_micro_ops_->bus_program = bus_error_steps_;
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 20:11:01 +00:00
Starts sketching out the asynchronous bus.
2019-04-29 17:45:53 +00:00
// Set initial state.
Adds BRA and Bcc.
2019-03-26 02:54:49 +00:00
active_step_ = reset_bus_steps_;
Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes. With only MOVEs from those to a data register implemented so far.
2019-03-19 02:51:32 +00:00
effective_address_[0] = 0;
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp. As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 23:41:07 +00:00
is_supervisor_ = 1;
ADD/SUBQ #, An shouldn't set flags. Also, temporarily at least, adds a new means for observing CPU behaviour.
2019-04-24 13:59:54 +00:00
interrupt_level_ = 7;
address_[7] = 0x00030000;
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-12 02:47:58 +00:00
}
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-18 01:57:00 +00:00
void CPU::MC68000::ProcessorStorage::write_back_stack_pointer() {
stack_pointers_[is_supervisor_] = address_[7];
}
void CPU::MC68000::ProcessorStorage::set_is_supervisor(bool is_supervisor) {
const int new_is_supervisor = is_supervisor ? 1 : 0;
if(new_is_supervisor != is_supervisor_) {
stack_pointers_[is_supervisor_] = address_[7];
is_supervisor_ = new_is_supervisor;
address_[7] = stack_pointers_[is_supervisor_];
}
}
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