2019-05-04 02:16:07 +00:00
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//
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// Macintosh.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 03/05/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "Macintosh.hpp"
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2019-05-04 16:33:27 +00:00
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#include <array>
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2019-05-08 16:34:26 +00:00
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#include "Keyboard.hpp"
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2019-05-08 04:12:19 +00:00
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#include "RealTimeClock.hpp"
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2019-05-08 16:34:26 +00:00
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#include "Video.hpp"
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2019-05-04 03:25:42 +00:00
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#include "../../CRTMachine.hpp"
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2019-05-28 19:17:03 +00:00
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//#define LOG_TRACE
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2019-05-04 02:16:07 +00:00
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#include "../../../Processors/68000/68000.hpp"
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#include "../../../Components/6522/6522.hpp"
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2019-05-06 01:55:34 +00:00
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#include "../../../Components/DiskII/IWM.hpp"
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2019-05-04 03:25:42 +00:00
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2019-05-04 02:39:09 +00:00
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#include "../../Utility/MemoryPacker.hpp"
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2019-05-04 02:16:07 +00:00
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2019-05-08 04:12:19 +00:00
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namespace {
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const int CLOCK_RATE = 7833600;
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}
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2019-05-04 02:16:07 +00:00
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namespace Apple {
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namespace Macintosh {
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class ConcreteMachine:
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public Machine,
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2019-05-04 03:25:42 +00:00
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public CRTMachine::Machine,
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2019-05-04 02:16:07 +00:00
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public CPU::MC68000::BusHandler {
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public:
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ConcreteMachine(const ROMMachine::ROMFetcher &rom_fetcher) :
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2019-05-04 03:25:42 +00:00
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mc68000_(*this),
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2019-05-04 16:33:27 +00:00
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video_(ram_.data()),
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2019-05-04 20:38:01 +00:00
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via_(via_port_handler_),
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2019-05-08 20:54:19 +00:00
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via_port_handler_(*this, clock_, keyboard_, video_),
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2019-05-08 04:12:19 +00:00
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iwm_(CLOCK_RATE) {
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2019-05-04 02:16:07 +00:00
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2019-05-04 02:39:09 +00:00
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// Grab a copy of the ROM and convert it into big-endian data.
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2019-05-04 02:16:07 +00:00
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const auto roms = rom_fetcher("Macintosh", { "mac128k.rom" });
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if(!roms[0]) {
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throw ROMMachine::Error::MissingROMs;
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}
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roms[0]->resize(64*1024);
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2019-05-04 16:33:27 +00:00
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Memory::PackBigEndian16(*roms[0], rom_.data());
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2019-05-04 03:25:42 +00:00
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// The Mac runs at 7.8336mHz.
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2019-05-08 04:12:19 +00:00
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set_clock_rate(double(CLOCK_RATE));
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2019-05-04 03:25:42 +00:00
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}
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) override {
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video_.set_scan_target(scan_target);
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}
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Outputs::Speaker::Speaker *get_speaker() override {
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return nullptr;
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}
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void run_for(const Cycles cycles) override {
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mc68000_.run_for(cycles);
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2019-05-04 02:16:07 +00:00
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}
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2019-05-04 16:33:27 +00:00
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
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2019-05-08 20:54:19 +00:00
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// time_since_video_update_ += cycle.length;
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2019-05-06 01:55:34 +00:00
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time_since_iwm_update_ += cycle.length;
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2019-05-05 02:27:58 +00:00
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2019-05-07 21:16:22 +00:00
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// The VIA runs at one-tenth of the 68000's clock speed, in sync with the E clock.
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// See: Guide to the Macintosh Hardware Family p149 (PDF p188).
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2019-05-04 16:33:27 +00:00
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via_clock_ += cycle.length;
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via_.run_for(via_clock_.divide(HalfCycles(10)));
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2019-05-08 17:58:52 +00:00
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// The keyboard also has a clock, albeit a very slow one.
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// Its clock and data lines are connected to the VIA.
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keyboard_clock_ += cycle.length;
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auto keyboard_ticks = keyboard_clock_.divide(HalfCycles(CLOCK_RATE / 100000));
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if(keyboard_ticks > HalfCycles(0)) {
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keyboard_.run_for(keyboard_ticks);
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via_.set_control_line_input(MOS::MOS6522::Port::B, MOS::MOS6522::Line::Two, keyboard_.get_data());
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via_.set_control_line_input(MOS::MOS6522::Port::B, MOS::MOS6522::Line::One, keyboard_.get_clock());
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}
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2019-05-07 21:16:22 +00:00
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// TODO: SCC is a divide-by-two.
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2019-05-04 16:33:27 +00:00
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2019-05-08 04:12:19 +00:00
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// Consider updating the real-time clock.
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real_time_clock_ += cycle.length;
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auto ticks = real_time_clock_.divide_cycles(Cycles(CLOCK_RATE)).as_int();
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while(ticks--) {
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clock_.update();
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// TODO: leave a delay between toggling the input rather than using this coupled hack.
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via_.set_control_line_input(MOS::MOS6522::Port::A, MOS::MOS6522::Line::Two, true);
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via_.set_control_line_input(MOS::MOS6522::Port::A, MOS::MOS6522::Line::Two, false);
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}
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2019-05-08 20:54:19 +00:00
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// Update the video. TODO: only on demand.
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video_.run_for(cycle.length);
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via_.set_control_line_input(MOS::MOS6522::Port::A, MOS::MOS6522::Line::One, video_.vsync());
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2019-05-08 04:12:19 +00:00
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// Update interrupt input. TODO: move this into a VIA/etc delegate callback?
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mc68000_.set_interrupt_level( (via_.get_interrupt_line() ? 1 : 0) );
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2019-05-04 16:33:27 +00:00
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// A null cycle leaves nothing else to do.
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if(cycle.operation) {
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auto word_address = cycle.word_address();
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2019-05-07 21:16:22 +00:00
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// Everything above E0 0000 is signalled as being on the peripheral bus.
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mc68000_.set_is_peripheral_address(word_address >= 0x700000);
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2019-05-06 18:10:13 +00:00
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2019-05-04 16:33:27 +00:00
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if(word_address >= 0x400000) {
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2019-05-04 18:23:37 +00:00
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if(cycle.data_select_active()) {
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2019-05-04 21:12:26 +00:00
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const int register_address = word_address >> 8;
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2019-05-07 02:57:29 +00:00
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switch(word_address & 0x78f000) {
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case 0x70f000:
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2019-05-04 20:38:01 +00:00
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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2019-05-04 21:12:26 +00:00
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cycle.value->halves.low = via_.get_register(register_address);
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2019-05-04 20:38:01 +00:00
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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2019-05-04 21:12:26 +00:00
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via_.set_register(register_address, cycle.value->halves.low);
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2019-05-04 20:38:01 +00:00
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}
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break;
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2019-05-07 02:57:29 +00:00
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case 0x68f000:
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2019-05-06 01:55:34 +00:00
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// The IWM; this is a purely polled device, so can be run on demand.
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iwm_.run_for(time_since_iwm_update_.flush_cycles());
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2019-05-05 22:12:25 +00:00
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if(cycle.operation & Microcycle::Read) {
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2019-05-06 01:55:34 +00:00
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cycle.value->halves.low = iwm_.read(register_address);
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2019-05-05 22:12:25 +00:00
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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2019-05-06 01:55:34 +00:00
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iwm_.write(register_address, cycle.value->halves.low);
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2019-05-05 22:12:25 +00:00
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}
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2019-05-04 20:38:01 +00:00
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break;
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2019-05-04 18:23:37 +00:00
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2019-05-07 01:32:10 +00:00
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default:
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if(cycle.operation & Microcycle::Read) {
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2019-05-28 19:17:03 +00:00
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// printf("Unrecognised read %06x\n", *cycle.address & 0xffffff);
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2019-05-08 20:54:19 +00:00
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cycle.value->halves.low = 0x00;
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2019-05-07 01:32:10 +00:00
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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break;
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}
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2019-05-04 18:23:37 +00:00
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}
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2019-05-04 16:33:27 +00:00
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} else {
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if(cycle.data_select_active()) {
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uint16_t *memory_base = nullptr;
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2019-05-07 21:16:22 +00:00
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auto operation = cycle.operation;
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2019-05-04 18:23:37 +00:00
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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2019-05-04 21:29:30 +00:00
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if(
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2019-05-07 21:16:22 +00:00
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(ROM_is_overlay_ && word_address >= 0x300000) ||
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(!ROM_is_overlay_ && word_address < 0x200000)
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2019-05-04 21:29:30 +00:00
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) {
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2019-05-04 16:33:27 +00:00
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memory_base = ram_.data();
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word_address %= ram_.size();
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2019-05-04 21:29:30 +00:00
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} else {
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memory_base = rom_.data();
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word_address %= rom_.size();
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2019-05-07 21:16:22 +00:00
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2019-05-08 19:07:03 +00:00
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// Disallow writes to ROM; also it doesn't mirror above 0x60000, ever.
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if(!(operation & Microcycle::Read) || word_address >= 0x300000) operation = 0;
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2019-05-04 16:33:27 +00:00
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}
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2019-05-07 21:16:22 +00:00
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switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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default:
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break;
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2019-05-04 21:29:30 +00:00
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift());
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break;
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case Microcycle::SelectWord:
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memory_base[word_address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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memory_base[word_address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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2019-05-06 02:48:40 +00:00
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(memory_base[word_address] & cycle.untouched_byte_mask())
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2019-05-04 21:29:30 +00:00
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);
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break;
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2019-05-04 16:33:27 +00:00
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}
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} else {
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2019-05-04 21:29:30 +00:00
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// TODO: add delay if this is a RAM access and video blocks it momentarily.
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// "Each [video] fetch took two cycles out of eight"
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2019-05-04 16:33:27 +00:00
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}
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}
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}
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2019-05-04 03:55:28 +00:00
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/*
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Normal memory map:
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000000: RAM
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400000: ROM
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9FFFF8+: SCC read operations
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BFFFF8+: SCC write operations
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DFE1FF+: IWM
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EFE1FE+: VIA
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*/
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2019-05-04 03:40:22 +00:00
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return HalfCycles(0);
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}
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2019-05-05 02:27:58 +00:00
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void flush() {
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2019-05-08 20:54:19 +00:00
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// video_.run_for(time_since_video_update_.flush());
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2019-05-05 02:27:58 +00:00
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}
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2019-05-04 03:40:22 +00:00
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2019-05-04 20:38:01 +00:00
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void set_rom_is_overlay(bool rom_is_overlay) {
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ROM_is_overlay_ = rom_is_overlay;
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}
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2019-05-06 03:05:24 +00:00
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void set_use_alternate_screen_buffer(bool use_alternate_screen_buffer) {
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video_.set_use_alternate_screen_buffer(use_alternate_screen_buffer);
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}
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2019-05-04 02:16:07 +00:00
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private:
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2019-05-04 20:38:01 +00:00
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class VIAPortHandler: public MOS::MOS6522::PortHandler {
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public:
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2019-05-08 20:54:19 +00:00
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VIAPortHandler(ConcreteMachine &machine, RealTimeClock &clock, Keyboard &keyboard, Video &video) :
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machine_(machine), clock_(clock), keyboard_(keyboard), video_(video) {}
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2019-05-04 20:38:01 +00:00
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2019-05-04 21:12:26 +00:00
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using Port = MOS::MOS6522::Port;
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using Line = MOS::MOS6522::Line;
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void set_port_output(Port port, uint8_t value, uint8_t direction_mask) {
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2019-05-04 20:38:01 +00:00
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/*
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Peripheral lines: keyboard data, interrupt configuration.
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(See p176 [/215])
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*/
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switch(port) {
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2019-05-04 21:12:26 +00:00
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case Port::A:
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2019-05-04 20:38:01 +00:00
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/*
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Port A:
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b7: [input] SCC wait/request (/W/REQA and /W/REQB wired together for a logical OR)
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b6: 0 = alternate screen buffer, 1 = main screen buffer
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b5: floppy disk SEL state control (upper/lower head "among other things")
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b4: 1 = use ROM overlay memory map, 0 = use ordinary memory map
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b3: 0 = use alternate sound buffer, 1 = use ordinary sound buffer
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b2–b0: audio output volume
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*/
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2019-05-07 01:32:10 +00:00
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|
|
// printf("6522 A: %02x\n", value);
|
2019-05-08 16:34:26 +00:00
|
|
|
|
|
2019-05-06 03:05:24 +00:00
|
|
|
|
machine_.set_use_alternate_screen_buffer(!(value & 0x40));
|
2019-05-08 16:34:26 +00:00
|
|
|
|
machine_.set_rom_is_overlay(!!(value & 0x10));
|
2019-05-04 20:38:01 +00:00
|
|
|
|
break;
|
|
|
|
|
|
2019-05-04 21:12:26 +00:00
|
|
|
|
case Port::B:
|
|
|
|
|
/*
|
|
|
|
|
Port B:
|
|
|
|
|
b7: 0 = sound enabled, 1 = sound disabled
|
|
|
|
|
b6: [input] 0 = video beam in visible portion of line, 1 = outside
|
|
|
|
|
b5: [input] mouse y2
|
|
|
|
|
b4: [input] mouse x2
|
|
|
|
|
b3: [input] 0 = mouse button down, 1 = up
|
|
|
|
|
b2: 0 = real-time clock enabled, 1 = disabled
|
|
|
|
|
b1: clock's data-clock line
|
|
|
|
|
b0: clock's serial data line
|
|
|
|
|
*/
|
2019-05-08 04:12:19 +00:00
|
|
|
|
if(value & 0x4) clock_.abort();
|
|
|
|
|
else clock_.set_input(!!(value & 0x2), !!(value & 0x1));
|
2019-05-04 20:38:01 +00:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-04 21:12:26 +00:00
|
|
|
|
uint8_t get_port_input(Port port) {
|
|
|
|
|
switch(port) {
|
|
|
|
|
case Port::A:
|
2019-05-07 01:32:10 +00:00
|
|
|
|
// printf("6522 r A\n");
|
2019-05-08 20:54:19 +00:00
|
|
|
|
return 0x00; // TODO: b7 = SCC wait/request
|
2019-05-04 21:12:26 +00:00
|
|
|
|
|
|
|
|
|
case Port::B:
|
2019-05-08 20:54:19 +00:00
|
|
|
|
return
|
|
|
|
|
(clock_.get_data() ? 0x02 : 0x00) |
|
|
|
|
|
(video_.is_outputting() ? 0x00 : 0x40);
|
|
|
|
|
// TODO: mouse button, y2, x2
|
2019-05-04 21:12:26 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void set_control_line_output(Port port, Line line, bool value) {
|
2019-05-08 04:12:19 +00:00
|
|
|
|
/*
|
|
|
|
|
Keyboard wiring (I believe):
|
2019-05-08 19:07:03 +00:00
|
|
|
|
CB2 = data (input/output)
|
2019-05-08 16:34:26 +00:00
|
|
|
|
CB1 = clock (input)
|
2019-05-08 04:12:19 +00:00
|
|
|
|
|
|
|
|
|
CA2 is used for receiving RTC interrupts.
|
2019-05-08 16:34:26 +00:00
|
|
|
|
CA1 is used for receiving vsync maybe?
|
2019-05-08 04:12:19 +00:00
|
|
|
|
*/
|
2019-05-08 16:34:26 +00:00
|
|
|
|
if(port == Port::B && line == Line::Two) keyboard_.set_input(value);
|
2019-05-04 21:12:26 +00:00
|
|
|
|
}
|
|
|
|
|
|
2019-05-04 20:38:01 +00:00
|
|
|
|
private:
|
|
|
|
|
ConcreteMachine &machine_;
|
2019-05-08 04:12:19 +00:00
|
|
|
|
RealTimeClock &clock_;
|
2019-05-08 16:34:26 +00:00
|
|
|
|
Keyboard &keyboard_;
|
2019-05-08 20:54:19 +00:00
|
|
|
|
Video &video_;
|
2019-05-04 03:40:22 +00:00
|
|
|
|
};
|
|
|
|
|
|
2019-05-04 16:33:27 +00:00
|
|
|
|
std::array<uint16_t, 32*1024> rom_;
|
|
|
|
|
std::array<uint16_t, 64*1024> ram_;
|
|
|
|
|
|
2019-05-04 02:16:07 +00:00
|
|
|
|
CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
|
2019-05-04 03:25:42 +00:00
|
|
|
|
Video video_;
|
2019-05-04 03:40:22 +00:00
|
|
|
|
|
2019-05-08 04:12:19 +00:00
|
|
|
|
RealTimeClock clock_;
|
2019-05-08 16:34:26 +00:00
|
|
|
|
Keyboard keyboard_;
|
2019-05-08 04:12:19 +00:00
|
|
|
|
|
2019-05-04 03:40:22 +00:00
|
|
|
|
MOS::MOS6522::MOS6522<VIAPortHandler> via_;
|
|
|
|
|
VIAPortHandler via_port_handler_;
|
2019-05-05 22:12:25 +00:00
|
|
|
|
|
2019-05-06 01:55:34 +00:00
|
|
|
|
Apple::IWM iwm_;
|
2019-05-05 22:12:25 +00:00
|
|
|
|
|
2019-05-04 16:33:27 +00:00
|
|
|
|
HalfCycles via_clock_;
|
2019-05-08 17:58:52 +00:00
|
|
|
|
HalfCycles real_time_clock_;
|
|
|
|
|
HalfCycles keyboard_clock_;
|
2019-05-08 20:54:19 +00:00
|
|
|
|
HalfCycles video_clock_;
|
|
|
|
|
// HalfCycles time_since_video_update_;
|
2019-05-06 01:55:34 +00:00
|
|
|
|
HalfCycles time_since_iwm_update_;
|
2019-05-04 03:40:22 +00:00
|
|
|
|
|
2019-05-04 16:33:27 +00:00
|
|
|
|
bool ROM_is_overlay_ = true;
|
2019-05-04 02:16:07 +00:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
using namespace Apple::Macintosh;
|
|
|
|
|
|
|
|
|
|
Machine *Machine::Macintosh(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
|
|
|
|
|
return new ConcreteMachine(rom_fetcher);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Machine::~Machine() {}
|