2024-03-19 15:34:10 +00:00
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//
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// Disassembler.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 19/03/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "OperationMapper.hpp"
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#include <string>
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#include <sstream>
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namespace InstructionSet::ARM {
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struct Operand {
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enum class Type {
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2024-03-19 15:42:41 +00:00
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Immediate, Register, RegisterList, None
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} type = Type::None;
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2024-03-19 15:34:10 +00:00
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uint32_t value = 0;
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// TODO: encode shifting
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operator std::string() const {
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return "";
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}
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};
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struct Instruction {
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Condition condition;
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enum class Operation {
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AND, EOR, SUB, RSB,
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ADD, ADC, SBC, RSC,
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TST, TEQ, CMP, CMN,
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ORR, MOV, BIC, MVN,
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B, BL,
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SWI,
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Undefined,
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} operation = Operation::Undefined;
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Operand destination, operand1, operand2;
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std::string to_string(uint32_t address) const {
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std::ostringstream result;
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// Treat all nevers as nops.
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if(condition == Condition::NV) {
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return "nop";
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}
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// Print operation.
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switch(operation) {
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case Operation::Undefined: return "undefined";
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case Operation::SWI: return "swi";
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2024-03-19 15:42:41 +00:00
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case Operation::B: result << "b"; break;
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case Operation::BL: result << "bl"; break;
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case Operation::AND: result << "and"; break;
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case Operation::EOR: result << "eor"; break;
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case Operation::SUB: result << "sub"; break;
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case Operation::RSB: result << "rsb"; break;
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case Operation::ADD: result << "add"; break;
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case Operation::ADC: result << "adc"; break;
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case Operation::SBC: result << "sbc"; break;
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case Operation::RSC: result << "rsc"; break;
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case Operation::TST: result << "tst"; break;
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case Operation::TEQ: result << "teq"; break;
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case Operation::CMP: result << "cmp"; break;
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case Operation::CMN: result << "cmn"; break;
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case Operation::ORR: result << "orr"; break;
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case Operation::MOV: result << "mov"; break;
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case Operation::BIC: result << "bic"; break;
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case Operation::MVN: result << "mvn"; break;
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}
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// If this is a branch, append the target and complete.
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if(operation == Operation::B || operation == Operation::BL) {
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result << " 0x" << std::hex << ((address + 8 + operand1.value) & 0x3fffffc);
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return result.str();
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}
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return result.str();
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}
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};
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template <Model model>
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struct Disassembler {
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Instruction last() {
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return instruction_;
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}
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bool should_schedule(Condition condition) {
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instruction_ = Instruction();
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instruction_.condition = condition;
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return true;
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}
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template <Flags> void perform(DataProcessing) {}
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template <Flags> void perform(Multiply) {}
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template <Flags> void perform(SingleDataTransfer) {}
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template <Flags> void perform(BlockDataTransfer) {}
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template <Flags f> void perform(Branch fields) {
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constexpr BranchFlags flags(f);
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instruction_.operation =
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(flags.operation() == BranchFlags::Operation::BL) ?
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Instruction::Operation::BL : Instruction::Operation::B;
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instruction_.operand1.type = Operand::Type::Immediate;
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instruction_.operand1.value = fields.offset();
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}
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template <Flags> void perform(CoprocessorRegisterTransfer) {}
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template <Flags> void perform(CoprocessorDataOperation) {}
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template <Flags> void perform(CoprocessorDataTransfer) {}
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void software_interrupt() {
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instruction_.operation = Instruction::Operation::SWI;
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}
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void unknown() {
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instruction_.operation = Instruction::Operation::Undefined;
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}
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private:
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Instruction instruction_;
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};
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}
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