6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 23:32:28 +00:00
Code Issues Projects Releases Wiki Activity
65ca931e83
CLK/Machines/Apple/AppleIIgs/AppleIIgs.cpp

964 lines
32 KiB
C++
Raw Normal View History

Adds the IIgs as a user-selectable machine. Albeit that there is no underlying machine yet.
2020-10-21 02:18:11 +00:00
//
// AppleIIgs.cpp
// Clock Signal
//
// Created by Thomas Harte on 20/10/2020.
// Copyright 2020 Thomas Harte. All rights reserved.
//
#include "AppleIIgs.hpp"
Adds activity indicators.
2020-11-14 23:00:06 +00:00
#include "../../../Activity/Source.hpp"
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
#include "../../MachineTypes.hpp"
#include "../../../Processors/65816/65816.hpp"
Adds the IIgs as a user-selectable machine. Albeit that there is no underlying machine yet.
2020-10-21 02:18:11 +00:00
#include "../../../Analyser/Static/AppleIIgs/Target.hpp"
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
#include "ADB.hpp"
Factors out the IIgs memory map logic. As testing would be rational.
2020-10-26 01:10:04 +00:00
#include "MemoryMap.hpp"
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
#include "Video.hpp"
Stubs in some of the sound GLU registers.
2020-11-05 02:29:44 +00:00
#include "Sound.hpp"
Edges towards a functioning IIgs memory map. Next up: making sure language and auxiliary switches apply. That should get something from the ROM.
2020-10-23 23:41:10 +00:00
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
#include "../../../Components/8530/z8530.hpp"
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-30 01:38:36 +00:00
#include "../../../Components/AppleClock/AppleClock.hpp"
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
#include "../../../Components/AudioToggle/AudioToggle.hpp"
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
#include "../../../Components/DiskII/IWM.hpp"
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
#include "../../../Components/DiskII/MacintoshDoubleDensityDrive.hpp"
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
#include "../../../Components/DiskII/DiskIIDrive.hpp"
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
#include "../../../Outputs/Speaker/Implementation/CompoundSource.hpp"
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
#include "../../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
Ensures RAM is zero-initialised, for now, to aid in repeatable bug finding.
2020-11-01 00:03:23 +00:00
#include "../../Utility/MemoryFuzzer.hpp"
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
#include "../../../ClockReceiver/JustInTime.hpp"
Switches to a mapping system that supports non-continuous regions, and is smaller.
2020-10-25 22:28:32 +00:00
#include <cassert>
#include <array>
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
namespace {
constexpr int CLOCK_RATE = 14318180;
}
Adds the IIgs as a user-selectable machine. Albeit that there is no underlying machine yet.
2020-10-21 02:18:11 +00:00
namespace Apple {
namespace IIgs {
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
class ConcreteMachine:
Adds activity indicators.
2020-11-14 23:00:06 +00:00
public Activity::Source,
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
public Apple::IIgs::Machine,
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
public MachineTypes::AudioProducer,
Takes a guess at the format of IIgs .po files; wires them through to the actual machine. ... which still declines to boot.
2020-11-12 23:01:26 +00:00
public MachineTypes::MediaTarget,
public MachineTypes::ScanProducer,
public MachineTypes::TimedMachine,
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
public CPU::MOS6502Esque::BusHandler<uint32_t> {
public:
ConcreteMachine(const Analyser::Static::AppleIIgs::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
m65816_(*this),
Ensures safe shutdown.
2020-11-13 02:44:51 +00:00
iwm_(CLOCK_RATE / 2),
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
drives35_{
Corrects IWM clocking.
2020-11-12 23:09:31 +00:00
{CLOCK_RATE / 2, true},
{CLOCK_RATE / 2, true}
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
},
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
drives525_{
{CLOCK_RATE / 2},
{CLOCK_RATE / 2}
},
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
sound_glu_(audio_queue_),
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
audio_toggle_(audio_queue_),
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
mixer_(sound_glu_, audio_toggle_),
speaker_(mixer_) {
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
set_clock_rate(double(CLOCK_RATE));
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
speaker_.set_input_rate(float(CLOCK_RATE) / float(audio_divider));
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
using Target = Analyser::Static::AppleIIgs::Target;
std::vector<ROMMachine::ROM> rom_descriptions;
const std::string machine_name = "AppleIIgs";
switch(target.model) {
case Target::Model::ROM00:
/* TODO */
case Target::Model::ROM01:
rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM01", "apple2gs.rom", 128*1024, 0x42f124b0);
break;
case Target::Model::ROM03:
rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM03", "apple2gs.rom2", 256*1024, 0xde7ddf29);
break;
}
Quick refactor: this clearly isn't a `VideoBase`, it's the full implementation.
2020-11-26 17:54:20 +00:00
rom_descriptions.push_back(video_->rom_description(Video::Video::CharacterROM::EnhancedIIe));
Migrates character ROM handling; supplies one for the IIgs.
2020-11-07 22:45:03 +00:00
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
const auto roms = rom_fetcher(rom_descriptions);
Migrates character ROM handling; supplies one for the IIgs.
2020-11-07 22:45:03 +00:00
if(!roms[0] || !roms[1]) {
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
throw ROMMachine::Error::MissingROMs;
}
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
rom_ = *roms[0];
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_character_rom(*roms[1]);
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
Adds means to force specific ROM 03 self tests.
2020-12-03 01:48:19 +00:00
// Run only the currently-interesting self test.
rom_[0x36402] = 2;
// rom_[0x36403] = 0x7c; // ROM_CHECKSUM [working, when hacks like this are removed]
// rom_[0x36404] = 0x6c;
// rom_[0x36403] = 0x82; // MOVIRAM [working]
// rom_[0x36404] = 0x67;
// rom_[0x36403] = 0x2c; // SOFT_SW [working]
// rom_[0x36404] = 0x6a;
// rom_[0x36403] = 0xe8; // RAM_ADDR [working]
// rom_[0x36404] = 0x6f;
// rom_[0x36403] = 0xc7; // FPI_SPEED [working]
// rom_[0x36404] = 0x6a;
// rom_[0x36403] = 0xd7; // SER_TST [broken]
// rom_[0x36404] = 0x68;
// rom_[0x36403] = 0xdc; // CLOCK [broken]
// rom_[0x36404] = 0x6c;
rom_[0x36403] = 0x1b; // BAT_RAM [broken]
rom_[0x36404] = 0x6e;
// rom_[0x36403] = 0x11; // FDB (/ADB?) [broken]
// rom_[0x36404] = 0x6f;
// rom_[0x36403] = 0x41; // SHADOW_TST [working]
// rom_[0x36404] = 0x6d;
// rom_[0x36403] = 0x09; // CUSTOM_IRQ [broken?]
// rom_[0x36404] = 0x6b;
// rom_[0x36403] = 0xf4; // DOC_EXEC
// rom_[0x36404] = 0x70;
// rom_[0x36403] = 0xab; // ECT_SEQ
// rom_[0x36404] = 0x64;
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
size_t ram_size = 0;
switch(target.memory_model) {
case Target::MemoryModel::TwoHundredAndFiftySixKB:
ram_size = 256;
break;
case Target::MemoryModel::OneMB:
Edges towards a functioning IIgs memory map. Next up: making sure language and auxiliary switches apply. That should get something from the ROM.
2020-10-23 23:41:10 +00:00
ram_size = 128 + 1024;
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
break;
case Target::MemoryModel::EightMB:
Edges towards a functioning IIgs memory map. Next up: making sure language and auxiliary switches apply. That should get something from the ROM.
2020-10-23 23:41:10 +00:00
ram_size = 128 + 8 * 1024;
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
break;
}
ram_.resize(ram_size * 1024);
Starts memory map test class, already finding a typo.
2020-10-26 01:31:21 +00:00
memory_.set_storage(ram_, rom_);
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_internal_ram(&ram_[ram_.size() - 128*1024]);
Stubs in a speed register.
2020-10-29 01:23:45 +00:00
Seems to do enough padding out to get me to my second failing ADB command. That's better than failing at the first.
2020-11-10 00:05:48 +00:00
// Select appropriate ADB behaviour.
adb_glu_.set_is_rom03(target.model == Target::Model::ROM03);
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
// Attach drives to the IWM.
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
iwm_->set_drive(0, &drives35_[0]);
iwm_->set_drive(1, &drives35_[1]);
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
Enables fuzzing, adds a definite no-op write.
2020-11-26 04:33:55 +00:00
// Randomise RAM contents.
Memory::Fuzz(ram_);
Ensures RAM is zero-initialised, for now, to aid in repeatable bug finding.
2020-11-01 00:03:23 +00:00
Stubs in a speed register.
2020-10-29 01:23:45 +00:00
// Sync up initial values.
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
memory_.set_speed_register(speed_register_ ^ 0x80);
Takes a guess at the format of IIgs .po files; wires them through to the actual machine. ... which still declines to boot.
2020-11-12 23:01:26 +00:00
insert_media(target.media);
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
}
Ensures safe shutdown.
2020-11-13 02:44:51 +00:00
~ConcreteMachine() {
audio_queue_.flush();
}
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
void run_for(const Cycles cycles) override {
m65816_.run_for(cycles);
}
Makes first, faltering steps towards video display.
2020-11-08 01:42:34 +00:00
void flush() {
video_.flush();
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
iwm_.flush();
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
AudioUpdater updater(this);
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
audio_queue_.perform();
Makes first, faltering steps towards video display.
2020-11-08 01:42:34 +00:00
}
void set_scan_target(Outputs::Display::ScanTarget *target) override {
video_->set_scan_target(target);
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
}
Outputs::Display::ScanStatus get_scaled_scan_status() const override {
Makes first, faltering steps towards video display.
2020-11-08 01:42:34 +00:00
return video_->get_scaled_scan_status() * 2.0f; // TODO: expose multiplier and divider via the JustInTime template?
}
void set_display_type(Outputs::Display::DisplayType display_type) final {
video_->set_display_type(display_type);
}
Outputs::Display::DisplayType get_display_type() const final {
return video_->get_display_type();
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
}
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
Outputs::Speaker::Speaker *get_speaker() final {
return &speaker_;
}
Takes a guess at the format of IIgs .po files; wires them through to the actual machine. ... which still declines to boot.
2020-11-12 23:01:26 +00:00
// MARK: MediaTarget.
bool insert_media(const Analyser::Static::Media &media) final {
if(!media.disks.empty()) {
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
const auto disk = media.disks[0];
if(disk->get_maximum_head_position().as_int() > 35) {
drives35_[0].set_disk(media.disks[0]);
} else {
drives525_[0].set_disk(media.disks[0]);
}
Takes a guess at the format of IIgs .po files; wires them through to the actual machine. ... which still declines to boot.
2020-11-12 23:01:26 +00:00
}
return true;
}
Adds activity indicators.
2020-11-14 23:00:06 +00:00
// MARK: Activity::Source
void set_activity_observer(Activity::Observer *observer) final {
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
drives35_[0].set_activity_observer(observer, "First 3.5\" Drive", true);
drives35_[1].set_activity_observer(observer, "Second 3.5\" Drive", true);
drives525_[0].set_activity_observer(observer, "First 5.25\" Drive", true);
drives525_[1].set_activity_observer(observer, "Second 5.25\" Drive", true);
Adds activity indicators.
2020-11-14 23:00:06 +00:00
}
Takes a guess at the format of IIgs .po files; wires them through to the actual machine. ... which still declines to boot.
2020-11-12 23:01:26 +00:00
// MARK: BusHandler.
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
Factors out the IIgs memory map logic. As testing would be rational.
2020-10-26 01:10:04 +00:00
const auto &region = MemoryMapRegion(memory_, address);
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
static bool log = false;
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
static uint64_t total = 0;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
bool is_1Mhz = false;
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
Adds guaranteed trip to ROM for vector pulls.
2020-11-30 02:29:15 +00:00
if(operation == CPU::WDC65816::BusOperation::ReadVector) {
// I think vector pulls always go to ROM?
// That's slightly implied in the documentation, and doing so makes GS/OS boot, so...
*value = rom_[rom_.size() - 65536 + address];
} else if(region.flags & MemoryMap::Region::IsIO) {
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
// Ensure classic auxiliary and language card accesses have effect.
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-30 01:38:36 +00:00
const bool is_read = isReadOperation(operation);
memory_.access(uint16_t(address), is_read);
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
// TODO: which of these are actually 2.8Mhz?
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
const auto address_suffix = address & 0xffff;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
#define ReadWrite(x) (x) | (is_read * 0x10000)
#define Read(x) (x) | 0x10000
#define Write(x) (x)
switch(ReadWrite(address_suffix)) {
Gets as far as seemingly yet another memory-map setting. Tomorrow, maybe?
2020-10-28 02:31:58 +00:00
// New video register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc029):
Throws in a new assert, against the unimplemented bit 0 of new video.
2020-12-07 01:26:24 +00:00
*value = video_->get_new_video();
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
break;
case Write(0xc029):
video_->set_new_video(*value);
Throws in a new assert, against the unimplemented bit 0 of new video.
2020-12-07 01:26:24 +00:00
assert(*value & 1);
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
// TODO: I think bits 7 and 0 might also affect the memory map.
// The descripton isn't especially clear — P.90 of the Hardware Reference.
// Revisit if necessary.
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
break;
// Video [and clock] interrupt register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc023):
*value = video_->get_interrupt_register();
break;
case Write(0xc023):
video_->set_interrupt_register(*value);
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
// Video interrupt-clear register.
case Write(0xc032):
video_->clear_interrupts(*value);
Gets as far as seemingly yet another memory-map setting. Tomorrow, maybe?
2020-10-28 02:31:58 +00:00
break;
Corrects counter scales, adds a read for $c032. Albeit that I have no idea what that's supposed to read as.
2020-11-30 01:08:59 +00:00
case Read(0xc032):
// TODO: this seems to be undocumented, but used. What value is likely?
*value = 0xff;
break;
Gets as far as seemingly yet another memory-map setting. Tomorrow, maybe?
2020-10-28 02:31:58 +00:00
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
// Shadow register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc035):
*value = memory_.get_shadow_register();
break;
case Write(0xc035):
memory_.set_shadow_register(*value);
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
break;
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-30 01:38:36 +00:00
// Clock data.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc033):
*value = clock_.get_data();
break;
case Write(0xc033):
clock_.set_data(*value);
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-30 01:38:36 +00:00
break;
// Clock and border control.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc034):
Resolves border colour resets.
2020-11-26 18:13:48 +00:00
*value = (clock_.get_control() & 0xf0) | (video_.last_valid()->get_border_colour() & 0x0f);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
break;
case Write(0xc034):
clock_.set_control(*value);
video_->set_border_colour(*value);
Adds text colour register. Oddly this isn't currently being set. So probably another latent fault elsewhere.
2020-11-08 04:14:50 +00:00
break;
// Colour text control.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Write(0xc022):
video_->set_text_colour(*value);
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-30 01:38:36 +00:00
break;
Stubs in a speed register.
2020-10-29 01:23:45 +00:00
// Speed register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc036):
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
*value = speed_register_ ^ 0x80;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
break;
case Write(0xc036):
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
// b7: 1 => operate at 2.8Mhz; 0 => 1Mhz.
// b6: power-on status; 1 => system has been turned on by the power switch (TODO: what clears this?)
// b5: reserved
// b4: [bank shadowing bit; cf. the memory map]
// b0–3: motor on-off speed detectors;
// 1 => switch to 1Mhz if motor is on; 0 => don't;
// b0 = slot 4 (i.e. watches addresses c0c9, c0c8)
// b1 = slot 5 (i.e. c0d9, c0d8)
// b2 = slot 6 (i.e. c0e9, c0e8)
// b3 = slot 7 (i.e. c0f9, c0f8)
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
memory_.set_speed_register(*value);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
speed_register_ = *value ^ 0x80;
Stubs in a speed register.
2020-10-29 01:23:45 +00:00
break;
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
// [Memory] State register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc068):
*value = memory_.get_state_register();
break;
case Write(0xc068):
memory_.set_state_register(*value);
Ensures that PAGE2 propagates from the state register to video.
2020-12-01 03:56:19 +00:00
video_->set_page2(*value & 0x40);
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
break;
Corrects interpretation of bit 3 of the state register. And attempts to be a bit more careful with the language card in general.
2020-11-05 02:15:10 +00:00
// Various independent memory switch reads [TODO: does the IIe-style keyboard provide the low seven?].
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
#define SwitchRead(s) *value = memory_.s ? 0x80 : 0x00; is_1Mhz = true;
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
#define LanguageRead(s) SwitchRead(language_card_switches().state().s)
#define AuxiliaryRead(s) SwitchRead(auxiliary_switches().switches().s)
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
#define VideoRead(s) *value = video_.last_valid()->s ? 0x80 : 0x00; is_1Mhz = true;
The soft switch is LCBANK2, not LCBANK1. [This also jimmys the IIgs into always entering its extended self test, for now]
2020-12-01 03:35:51 +00:00
case Read(0xc011): LanguageRead(bank2); break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc012): LanguageRead(read); break;
case Read(0xc013): AuxiliaryRead(read_auxiliary_memory); break;
case Read(0xc014): AuxiliaryRead(write_auxiliary_memory); break;
case Read(0xc015): AuxiliaryRead(internal_CX_rom); break;
case Read(0xc016): AuxiliaryRead(alternative_zero_page); break;
case Read(0xc017): AuxiliaryRead(slot_C3_rom); break;
case Read(0xc018): VideoRead(get_80_store()); break;
Reduces frequency of video flushes.
2020-11-17 02:55:41 +00:00
case Read(0xc019):
VideoRead(get_is_vertical_blank(video_.time_since_flush()));
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc01a): VideoRead(get_text()); break;
case Read(0xc01b): VideoRead(get_mixed()); break;
case Read(0xc01c): VideoRead(get_page2()); break;
case Read(0xc01d): VideoRead(get_high_resolution()); break;
case Read(0xc01e): VideoRead(get_alternative_character_set()); break;
case Read(0xc01f): VideoRead(get_80_columns()); break;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
#undef VideoRead
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
#undef AuxiliaryRead
#undef LanguageRead
#undef SwitchRead
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// Video switches (and annunciators).
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc050): case Read(0xc051):
case Write(0xc050): case Write(0xc051):
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_text(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc052): case Read(0xc053):
case Write(0xc052): case Write(0xc053):
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_mixed(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc054): case Read(0xc055):
case Write(0xc054): case Write(0xc055):
Ensures that PAGE2 propagates from the state register to video.
2020-12-01 03:56:19 +00:00
video_->set_page2(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc056): case Read(0xc057):
case Write(0xc056): case Write(0xc057):
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_high_resolution(address&1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc058): case Read(0xc059):
case Write(0xc058): case Write(0xc059):
case Read(0xc05a): case Read(0xc05b):
case Write(0xc05a): case Write(0xc05b):
case Read(0xc05c): case Read(0xc05d):
case Write(0xc05c): case Write(0xc05d):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// Annunciators 0, 1 and 2.
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc05e): case Read(0xc05f):
case Write(0xc05e): case Write(0xc05f):
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_->set_annunciator_3(!(address&1));
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Write(0xc000): case Write(0xc001):
video_->set_80_store(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Write(0xc00c): case Write(0xc00d):
video_->set_80_columns(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Write(0xc00e): case Write(0xc00f):
video_->set_alternative_character_set(address & 1);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Stubs in $c010. Also reduces memory map logging.
2020-11-05 02:35:11 +00:00
// ADB and keyboard.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc000):
*value = adb_glu_.get_keyboard_data();
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc010):
*value = adb_glu_.get_any_key_down() ? 0x80 : 0x00;
[[fallthrough]];
case Write(0xc010):
Stubs in $c010. Also reduces memory map logging.
2020-11-05 02:35:11 +00:00
adb_glu_.clear_key_strobe();
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc024):
*value = adb_glu_.get_mouse_data();
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc025):
*value = adb_glu_.get_modifier_status();
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc026):
*value = adb_glu_.get_data();
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Write(0xc026):
adb_glu_.set_command(*value);
break;
case Read(0xc027):
*value = adb_glu_.get_status();
break;
case Write(0xc027):
adb_glu_.set_status(*value);
Stubs in the ADB GLU.
2020-11-01 01:00:15 +00:00
break;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
// The SCC.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc038): case Read(0xc039): case Read(0xc03a): case Read(0xc03b):
*value = scc_.read(int(address));
break;
case Write(0xc038): case Write(0xc039): case Write(0xc03a): case Write(0xc03b):
scc_.write(int(address), *value);
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
break;
Stubs in some of the sound GLU registers.
2020-11-05 02:29:44 +00:00
// The audio GLU.
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
case Read(0xc03c): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = sound_glu_.get_control();
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Write(0xc03c): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
sound_glu_.set_control(*value);
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Read(0xc03d): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = sound_glu_.get_data();
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Write(0xc03d): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
sound_glu_.set_data(*value);
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Read(0xc03e): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = sound_glu_.get_address_low();
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Write(0xc03e): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
sound_glu_.set_address_low(*value);
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Read(0xc03f): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = sound_glu_.get_address_high();
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
case Write(0xc03f): {
AudioUpdater updater(this);
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
sound_glu_.set_address_high(*value);
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
Stubs in some of the sound GLU registers.
2020-11-05 02:29:44 +00:00
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
// These were all dealt with by the call to memory_.access.
// TODO: subject to read data? Does vapour lock apply?
Ensures that auxiliary/language-card soft switches don't trigger my assert.
2020-11-30 02:32:24 +00:00
case Read(0xc002): case Read(0xc003): case Read(0xc004): case Read(0xc005):
case Read(0xc006): case Read(0xc007): case Read(0xc008): case Read(0xc009): case Read(0xc00a): case Read(0xc00b):
*value = 0xff;
break;
case Write(0xc002): case Write(0xc003): case Write(0xc004): case Write(0xc005):
case Write(0xc006): case Write(0xc007): case Write(0xc008): case Write(0xc009): case Write(0xc00a): case Write(0xc00b):
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
break;
Maps in "the interrupt ROM addresses".
2020-10-31 01:42:43 +00:00
// Interrupt ROM addresses; Cf. P25 of the Hardware Reference.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc071): case Read(0xc072): case Read(0xc073):
case Read(0xc074): case Read(0xc075): case Read(0xc076): case Read(0xc077):
case Read(0xc078): case Read(0xc079): case Read(0xc07a): case Read(0xc07b):
case Read(0xc07c): case Read(0xc07d): case Read(0xc07e): case Read(0xc07f):
*value = rom_[rom_.size() - 65536 + address_suffix];
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
// Analogue inputs. All TODO.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc060): case Read(0xc061): case Read(0xc062): case Read(0xc063):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// Joystick buttons (and keyboard modifiers).
Throws in a new assert, against the unimplemented bit 0 of new video.
2020-12-07 01:26:24 +00:00
*value = 0x00;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc064): case Read(0xc065): case Read(0xc066): case Read(0xc067):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// Analogue inputs.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = 0x00;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc070): case Write(0xc070):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// TODO: begin analogue channel charge.
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
// Monochome/colour register.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc021):
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
// "Uses bit 7 to determine whether composite output is colour 9) or gray scale (1)."
Takes a shot at the two video counter registers.
2020-11-30 00:57:35 +00:00
*value = video_.last_valid()->get_composite_is_colour() ? 0x00 : 0x80;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
break;
case Write(0xc021):
video_->set_composite_is_colour(!(*value & 0x80));
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
break;
Takes a shot at the two video counter registers.
2020-11-30 00:57:35 +00:00
case Read(0xc02e):
*value = video_.last_valid()->get_vertical_counter(video_.time_since_flush());
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the two video counter registers.
2020-11-30 00:57:35 +00:00
break;
case Read(0xc02f):
*value = video_.last_valid()->get_horizontal_counter(video_.time_since_flush());
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the two video counter registers.
2020-11-30 00:57:35 +00:00
break;
Gets a bit more rigorous in remaining missing parts.
2020-11-27 03:36:32 +00:00
// case Read(0xc037): case Write(0xc037):
// // TODO: "Used during DMA as bank address"?
// break;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
case Read(0xc041):
*value = megaii_interrupt_mask_;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Write(0xc041):
megaii_interrupt_mask_ = *value;
video_->set_megaii_interrupts_enabled(*value);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Read(0xc044):
// MMDELTAX byte.
*value = 0;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Read(0xc045):
// MMDELTAX byte.
*value = 0;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Read(0xc046):
*value = video_->get_megaii_interrupt_status();
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Read(0xc047): case Write(0xc047):
video_->clear_megaii_interrupts();
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
case Read(0xc048): case Write(0xc048):
// No-op: Clear Mega II mouse interrupt flags
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = true;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
break;
Gets a bit more rigorous in remaining missing parts.
2020-11-27 03:36:32 +00:00
// Language select.
// b7, b6, b5: character generator language select;
// b4: NTSC/PAL (0 = NTC);
// b3: language select — primary or secondary.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc02b):
*value = language_;
break;
case Write(0xc02b):
language_ = *value;
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
break;
Gets a bit more rigorous in remaining missing parts.
2020-11-27 03:36:32 +00:00
// TODO: 0xc02c is "Addr for tst mode read of character ROM". So it reads... what?
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
// Slot select.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc02d):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// b7: 0 = internal ROM code for slot 7;
// b6: 0 = internal ROM code for slot 6;
// b5: 0 = internal ROM code for slot 5;
// b4: 0 = internal ROM code for slot 4;
// b3: reserved;
// b2: internal ROM code for slot 2;
// b1: internal ROM code for slot 1;
// b0: reserved.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
*value = card_mask_;
break;
case Write(0xc02d):
card_mask_ = *value;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
break;
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
case Read(0xc030): case Write(0xc030): {
AudioUpdater updater(this);
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
audio_toggle_.set_output(!audio_toggle_.get_output());
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
} break;
Stubs in audio toggle and disk control. It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-10 03:21:52 +00:00
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// 'Test Mode', whatever that is (?)
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc06e): case Read(0xc06f):
case Write(0xc06e): case Write(0xc06f):
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
test_mode_ = address & 1;
break;
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc06d):
*value = test_mode_ * 0x80;
Maps in "the interrupt ROM addresses".
2020-10-31 01:42:43 +00:00
break;
Stubs in audio toggle and disk control. It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-10 03:21:52 +00:00
// Disk drive controls additional to the IWM.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
case Read(0xc031):
*value = disk_select_;
break;
case Write(0xc031):
Stubs in audio toggle and disk control. It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-10 03:21:52 +00:00
// b7: 0 = use head 0; 1 = use head 1.
// b6: 0 = use 5.25" disks; 1 = use 3.5".
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
disk_select_ = *value;
iwm_->set_select(*value & 0x80);
// Presumably bit 6 selects between two 5.25" drives rather than the two 3.5"?
if(*value & 0x40) {
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
iwm_->set_drive(0, &drives35_[0]);
iwm_->set_drive(1, &drives35_[1]);
Also attaches IWM select line.
2020-11-10 23:59:23 +00:00
} else {
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
iwm_->set_drive(0, &drives525_[0]);
iwm_->set_drive(1, &drives525_[1]);
Also attaches IWM select line.
2020-11-10 23:59:23 +00:00
}
Stubs in audio toggle and disk control. It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-10 03:21:52 +00:00
break;
Enables fuzzing, adds a definite no-op write.
2020-11-26 04:33:55 +00:00
// Addresses on other Apple II devices which do nothing on the GS.
Gets a bit more rigorous in remaining missing parts.
2020-11-27 03:36:32 +00:00
case Read(0xc020): case Write(0xc020): // Reserved for future system expansion.
case Read(0xc028): case Write(0xc028): // ROMBANK; "not used in Apple IIGS".
case Read(0xc02a): case Write(0xc02a): // Reserved for future system expansion.
case Read(0xc040): case Write(0xc040): // Reserved for future system expansion.
case Read(0xc042): case Write(0xc042): // Reserved for future system expansion.
case Read(0xc043): case Write(0xc043): // Reserved for future system expansion.
case Read(0xc049): case Write(0xc049): // Reserved for future system expansion.
case Read(0xc04a): case Write(0xc04a): // Reserved for future system expansion.
case Read(0xc04b): case Write(0xc04b): // Reserved for future system expansion.
case Read(0xc04c): case Write(0xc04c): // Reserved for future system expansion.
case Read(0xc04d): case Write(0xc04d): // Reserved for future system expansion.
case Read(0xc04e): case Write(0xc04e): // Reserved for future system expansion.
case Read(0xc04f): case Write(0xc04f): // Reserved for future system expansion.
case Read(0xc06b): case Write(0xc06b): // Reserved for future system expansion.
case Read(0xc06c): case Write(0xc06c): // Reserved for future system expansion.
Enables fuzzing, adds a definite no-op write.
2020-11-26 04:33:55 +00:00
case Write(0xc07e):
break;
Gets as far as seemingly yet another memory-map setting. Tomorrow, maybe?
2020-10-28 02:31:58 +00:00
default:
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
// Update motor mask bits.
switch(address_suffix) {
case 0xc0c8: motor_flags_ &= ~0x01; break;
case 0xc0c9: motor_flags_ |= 0x01; break;
case 0xc0d8: motor_flags_ &= ~0x02; break;
case 0xc0d9: motor_flags_ |= 0x02; break;
case 0xc0e8: motor_flags_ &= ~0x04; break;
case 0xc0e9: motor_flags_ |= 0x04; break;
case 0xc0f8: motor_flags_ &= ~0x08; break;
case 0xc0f9: motor_flags_ |= 0x08; break;
}
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// Check for a card access.
if(address_suffix >= 0xc080 && address_suffix < 0xc800) {
// This is an abridged version of the similar code in AppleII.cpp from
// line 653; it would be good to factor that out and support cards here.
// For now just either supply the internal ROM or nothing as per the
// current card mask.
size_t card_number = 0;
Corrects card mask test outside of bank $00.
2020-11-22 03:22:27 +00:00
if(address_suffix >= 0xc100) {
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
/*
Decode the area conventionally used by cards for ROMs:
0xCn00 to 0xCnff: card n.
*/
Corrects card mask test outside of bank $00.
2020-11-22 03:22:27 +00:00
card_number = (address_suffix - 0xc000) >> 8;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
} else {
/*
Decode the area conventionally used by cards for registers:
C0n0 to C0nF: card n - 8.
*/
Corrects card mask test outside of bank $00.
2020-11-22 03:22:27 +00:00
card_number = (address_suffix - 0xc080) >> 4;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
}
const uint8_t permitted_card_mask_ = card_mask_ & 0xf6;
if(permitted_card_mask_ & (1 << card_number)) {
// TODO: Access an actual card.
Adds a bonus debugging assert. Let's see.
2020-11-30 23:15:02 +00:00
assert(operation != CPU::WDC65816::BusOperation::ReadOpcode);
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
if(is_read) {
*value = 0xff;
}
} else {
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
switch(address_suffix) {
default:
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
// Temporary: log _potential_ mistakes.
if(address_suffix < 0xc100) {
printf("Internal card-area access: %04x\n", address_suffix);
log |= operation == CPU::WDC65816::BusOperation::ReadOpcode;
}
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
if(is_read) {
*value = rom_[rom_.size() - 65536 + address_suffix];
}
break;
// IWM.
case 0xc0e0: case 0xc0e1: case 0xc0e2: case 0xc0e3:
case 0xc0e4: case 0xc0e5: case 0xc0e6: case 0xc0e7:
case 0xc0e8: case 0xc0e9: case 0xc0ea: case 0xc0eb:
case 0xc0ec: case 0xc0ed: case 0xc0ee: case 0xc0ef:
if(is_read) {
*value = iwm_->read(int(address_suffix));
} else {
iwm_->write(int(address_suffix), *value);
}
break;
}
Corrects interpretation of bit 3 of the state register. And attempts to be a bit more careful with the language card in general.
2020-11-05 02:15:10 +00:00
// log = true;
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
}
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
#undef ReadWrite
#undef Read
#undef Write
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
} else {
For now, at least, c800–cfff is always built-in ROM. Otherwise I probably need to extend my c3 logic to cover the other built-in cards (?)
2020-11-19 00:49:45 +00:00
// Access the internal ROM.
//
// TODO: should probably occur only if there was a preceding access to a built-in
// card ROM?
if(is_read) {
*value = rom_[rom_.size() - 65536 + address_suffix];
}
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
if(address_suffix < 0xc080) {
// TODO: all other IO accesses.
Collapses nested conditionals.
2020-11-14 23:23:31 +00:00
printf("Unhandled IO %s: %04x\n", is_read ? "read" : "write", address_suffix);
The soft switch is LCBANK2, not LCBANK1. [This also jimmys the IIgs into always entering its extended self test, for now]
2020-12-01 03:35:51 +00:00
// assert(false);
Exposes much of the auxiliary and language card stuff to the IIgs bus.
2020-10-29 01:58:20 +00:00
}
}
Gets as far as seemingly yet another memory-map setting. Tomorrow, maybe?
2020-10-28 02:31:58 +00:00
}
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
} else {
Increases logging substantially.
2020-10-31 00:11:55 +00:00
// For debugging purposes; if execution heads off into an unmapped page then
// it's pretty certain that my 65816 still has issues.
assert(operation != CPU::WDC65816::BusOperation::ReadOpcode || region.read);
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
is_1Mhz = region.flags & MemoryMap::Region::Is1Mhz;
Increases logging substantially.
2020-10-31 00:11:55 +00:00
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
if(isReadOperation(operation)) {
Factors out the IIgs memory map logic. As testing would be rational.
2020-10-26 01:10:04 +00:00
MemoryMapRead(region, address, value);
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
} else {
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
// Shadowed writes also occur "at 1Mhz".
// TODO: this is probably an approximation. I'm assuming that there's the ability asynchronously to post
// both a 1Mhz cycle and a 2.8Mhz cycle and since the latter always fits into the former, this is sufficiently
// descriptive. I suspect this isn't true as it wouldn't explain the speed boost that Wolfenstein and others
// get by adding periodic NOPs within their copy-to-shadow step.
//
// Maybe the interaction with 2.8Mhz refresh isn't as straightforward as I think?
is_1Mhz |= region.flags & MemoryMap::Region::IsShadowed;
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
// Use a very broad test for flushing video: any write to $e0 or $e1, or any write that is shadowed.
// TODO: at least restrict the e0/e1 test to possible video buffers!
if((address >= 0xe00000 && address < 0xe1000000) || region.flags & MemoryMap::Region::IsShadowed) {
video_.flush();
}
Factors out the IIgs memory map logic. As testing would be rational.
2020-10-26 01:10:04 +00:00
MemoryMapWrite(memory_, region, address, value);
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
}
}
Corrects interpretation of bit 3 of the state register. And attempts to be a bit more careful with the language card in general.
2020-11-05 02:15:10 +00:00
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
assert(address);
Shifts size-limiting of X and Y to transitions and mutations, away from reads. Primarily to remove potential bug-causing complexity — this is easier to debug. But let's see.
2020-11-05 01:35:41 +00:00
}
The soft switch is LCBANK2, not LCBANK1. [This also jimmys the IIgs into always entering its extended self test, for now]
2020-12-01 03:35:51 +00:00
// if(address >= 0xE11700 && address < 0xe11b00) {
Attempts a 'full' model of 2.8Mhz access timing. i.e. full to my current understanding.
2020-11-15 00:10:41 +00:00
// printf("%06x %s %02x%s\n", address, isReadOperation(operation) ? "->" : "<-", *value,
// operation == CPU::WDC65816::BusOperation::ReadOpcode ? " [*]" : "");
// }
Adds means to force specific ROM 03 self tests.
2020-12-03 01:48:19 +00:00
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
log = (address >= 0xff6cdc) && (address < 0xff6d43);
}
Ensures that PAGE2 propagates from the state register to video.
2020-12-01 03:56:19 +00:00
// log &= !((operation == CPU::WDC65816::BusOperation::ReadOpcode) && ((address < 0xff6a2c) || (address >= 0xff6a9c)));
Slightly reduces logging. Hopefully soon I can tear the whole lot out.
2020-11-17 02:46:19 +00:00
if(log) {
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
printf("%06x %s %02x [%s]", address, isReadOperation(operation) ? "->" : "<-", *value, (is_1Mhz || (speed_register_ & motor_flags_)) ? "1.0" : "2.8");
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
printf(" a:%04x x:%04x y:%04x s:%04x e:%d p:%02x db:%02x pb:%02x d:%04x [tot:%llu]\n",
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
m65816_.get_value_of_register(CPU::WDC65816::Register::A),
m65816_.get_value_of_register(CPU::WDC65816::Register::X),
m65816_.get_value_of_register(CPU::WDC65816::Register::Y),
m65816_.get_value_of_register(CPU::WDC65816::Register::StackPointer),
m65816_.get_value_of_register(CPU::WDC65816::Register::EmulationFlag),
m65816_.get_value_of_register(CPU::WDC65816::Register::Flags),
m65816_.get_value_of_register(CPU::WDC65816::Register::DataBank),
m65816_.get_value_of_register(CPU::WDC65816::Register::ProgramBank),
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
m65816_.get_value_of_register(CPU::WDC65816::Register::Direct),
Adds a bonus debugging assert. Let's see.
2020-11-30 23:15:02 +00:00
static_cast<unsigned long long>(total)
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
);
} else printf("\n");
}
Increases logging substantially.
2020-10-31 00:11:55 +00:00
Adds means to force specific ROM 03 self tests.
2020-12-03 01:48:19 +00:00
// Automatic test overrides.
// if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
// // SCC.
// if(address == 0xff68d7) *value = 0x18; // CLC
// if(address == 0xff68d8) *value = 0x6b; // RTL
//
// // Clock.
// if(address == 0xff68d7) *value = 0x18; // CLC
// if(address == 0xff68d8) *value = 0x6b; // RTL
// }
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
Cycles duration;
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
// In preparation for this test: the top bit of speed_register_ has been inverted,
// so 1 => 1Mhz, 0 => 2.8Mhz, and motor_flags_ always has that bit set.
if(is_1Mhz || (speed_register_ & motor_flags_)) {
Attempts also to implement 1Mhz access costs. Subject to TODO, and same observation as before: this is as to my current understanding only.
2020-11-15 00:23:01 +00:00
// TODO: this is very implicitly linked to the video timing; make that overt somehow. Even if it's just with a redundant video setter at construction.
const int current_length = 14 + 2*(slow_access_phase_ / 896); // Length of cycle currently ongoing.
const int phase_adjust = (current_length - slow_access_phase_%14)%current_length; // Amount of time to expand waiting until end of cycle, if not actually at start.
const int access_phase = (slow_access_phase_ + phase_adjust)%912; // Phase at which access will begin.
const int next_length = 14 + 2*(access_phase / 896); // Length of cycle that this access will occur within.
duration = Cycles(next_length + phase_adjust);
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
} else {
Attempts a 'full' model of 2.8Mhz access timing. i.e. full to my current understanding.
2020-11-15 00:10:41 +00:00
// Clues as to 'fast' refresh timing:
//
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
// (i) "The time required for the refresh cycles reduces the effective
// processor speed for programs in RAM by about 8 percent.";
Attempts a 'full' model of 2.8Mhz access timing. i.e. full to my current understanding.
2020-11-15 00:10:41 +00:00
// (ii) "These cycles occur approximately every 3.5 microseconds"
//
// 3.5µs @ 14,318,180Hz => one every 50.11 cycles. Safe to assume every 10th fast cycle
// is refresh? That feels like a lot.
//
// (and the IIgs is smart enough that refresh is applicable only to RAM accesses).
const int phase_adjust = (5 - fast_access_phase_%5)%5;
const int refresh = (fast_access_phase_ / 45) * bool(region.write) * 5;
duration = Cycles(5 + phase_adjust + refresh);
Steps towards proper calculation of time.
2020-11-14 23:39:16 +00:00
}
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
// TODO: lookup tables to avoid the above? LCM of the two phases is 22,800 so probably 912+50 bytes plus two counters.
Attempts a 'full' model of 2.8Mhz access timing. i.e. full to my current understanding.
2020-11-15 00:10:41 +00:00
fast_access_phase_ = (fast_access_phase_ + duration.as<int>()) % 50;
Attempts also to implement 1Mhz access costs. Subject to TODO, and same observation as before: this is as to my current understanding only.
2020-11-15 00:23:01 +00:00
slow_access_phase_ = (slow_access_phase_ + duration.as<int>()) % 912;
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
// Propagate time far and wide.
cycles_since_clock_tick_ += duration;
auto ticks = cycles_since_clock_tick_.divide(Cycles(CLOCK_RATE)).as_integral();
while(ticks--) {
clock_.update();
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_.last_valid()->notify_clock_tick(); // The video controller marshalls the one-second interrupt.
Adds notes to self; implements get_next_sequence_point for video, allowing per-line interrupts.
2020-11-16 19:42:50 +00:00
// TODO: I think I may have made a false assumption here; does
// the VGC have an independent 1-second interrupt?
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
update_interrupts();
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
}
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
video_ += duration;
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
iwm_ += duration;
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
cycles_since_audio_update_ += duration;
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 21:08:29 +00:00
total += decltype(total)(duration.as_integral());
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
if(cycles_since_audio_update_ >= cycles_until_audio_event_) {
AudioUpdater updater(this);
update_interrupts();
}
Ensures video interrupts can't be missed by a suitably-timed access.
2020-11-26 21:11:03 +00:00
if(video_.did_flush()) {
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
update_interrupts();
}
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
return duration;
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
}
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
void update_interrupts() {
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
// Update the interrupt line.
// TODO: are there other interrupt sources?
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
m65816_.set_irq_line(video_.last_valid()->get_interrupt_line() || sound_glu_.get_interrupt_line());
Switches to just-in-time video, for easy access to a clock divider.
2020-11-08 00:40:26 +00:00
}
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
private:
CPU::WDC65816::Processor<ConcreteMachine, false> m65816_;
Factors out the IIgs memory map logic. As testing would be rational.
2020-10-26 01:10:04 +00:00
MemoryMap memory_;
Stubs video switches into the IIgs.
2020-11-01 00:39:32 +00:00
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// MARK: - Timing.
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
int fast_access_phase_ = 0;
int slow_access_phase_ = 0;
Adds power-on bit to speed register.
2020-10-31 01:50:39 +00:00
uint8_t speed_register_ = 0x40; // i.e. Power-on status. (TODO: only if ROM03?)
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 22:46:30 +00:00
uint8_t motor_flags_ = 0x80;
Stubs in a speed register.
2020-10-29 01:23:45 +00:00
Switches to a mapping system that supports non-continuous regions, and is smaller.
2020-10-25 22:28:32 +00:00
// MARK: - Memory storage.
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
Ensures RAM is zero-initialised, for now, to aid in repeatable bug finding.
2020-11-01 00:03:23 +00:00
std::vector<uint8_t> ram_{};
Edges towards a working memory subsystem. At least structurally.
2020-10-22 23:25:04 +00:00
std::vector<uint8_t> rom_;
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
// MARK: - Other components.
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
Apple::Clock::ParallelClock clock_;
Quick refactor: this clearly isn't a `VideoBase`, it's the full implementation.
2020-11-26 17:54:20 +00:00
JustInTimeActor<Apple::IIgs::Video::Video, 1, 2, Cycles> video_; // i.e. run video at 7Mhz.
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
Apple::IIgs::ADB::GLU adb_glu_;
Connects up an SCC. Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
2020-10-29 02:07:34 +00:00
Zilog::SCC::z8530 scc_;
Corrects IWM clocking.
2020-11-12 23:09:31 +00:00
JustInTimeActor<Apple::IWM, 1, 2, Cycles> iwm_;
Attempts to do just enough with video to get a functioning vertical blank query.
2020-11-05 22:56:20 +00:00
Cycles cycles_since_clock_tick_;
Attempts to add 5.25" drive support to the IIgs. I want to try some classic software.
2020-11-21 02:37:17 +00:00
Apple::Macintosh::DoubleDensityDrive drives35_[2];
Apple::Disk::DiskIIDrive drives525_[2];
Makes a first effort at attaching an IWM.
2020-11-10 23:38:23 +00:00
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
// The audio parts.
Concurrency::DeferringAsyncTaskQueue audio_queue_;
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
Apple::IIgs::Sound::GLU sound_glu_;
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
Audio::Toggle audio_toggle_;
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
using AudioSource = Outputs::Speaker::CompoundSource<Apple::IIgs::Sound::GLU, Audio::Toggle>;
AudioSource mixer_;
Outputs::Speaker::LowpassSpeaker<AudioSource> speaker_;
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
Cycles cycles_since_audio_update_;
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
Cycles cycles_until_audio_event_;
Attempts the two most basic forms of DOC output. Sans interrupts. Or register reads of any variety.
2020-11-20 02:19:27 +00:00
static constexpr int audio_divider = 16;
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
void update_audio() {
Starts in the direction of audio support.
2020-11-18 23:39:11 +00:00
const auto divided_cycles = cycles_since_audio_update_.divide(Cycles(audio_divider));
sound_glu_.run_for(divided_cycles);
speaker_.run_for(audio_queue_, divided_cycles);
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
}
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 22:14:46 +00:00
class AudioUpdater {
public:
AudioUpdater(ConcreteMachine *machine) : machine_(machine) {
machine_->update_audio();
}
~AudioUpdater() {
machine_->cycles_until_audio_event_ = machine_->sound_glu_.get_next_sequence_point();
}
private:
ConcreteMachine *machine_;
};
friend AudioUpdater;
Adds the Apple II toggle speaker.
2020-11-12 02:04:38 +00:00
Attempts retroactively to enforce the rule that 8-bit index modes => no top byte. (Rather than a preserved but ignored top byte)
2020-11-02 23:55:28 +00:00
// MARK: - Cards.
// TODO: most of cards.
uint8_t card_mask_ = 0x00;
bool test_mode_ = false;
Stubs in a couple more registers. PC now hits $0000. Likely a bug.
2020-11-10 02:54:25 +00:00
uint8_t language_ = 0;
Also attaches IWM select line.
2020-11-10 23:59:23 +00:00
uint8_t disk_select_ = 0;
Takes a shot at the Mega II-style video interrupts.
2020-11-30 02:21:46 +00:00
uint8_t megaii_interrupt_mask_ = 0;
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
};
Adds the IIgs as a user-selectable machine. Albeit that there is no underlying machine yet.
2020-10-21 02:18:11 +00:00
}
}
using namespace Apple::IIgs;
Machine *Machine::AppleIIgs(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
Adds just enough to get a 65816 ticking over.
2020-10-22 01:19:18 +00:00
return new ConcreteMachine(*dynamic_cast<const Analyser::Static::AppleIIgs::Target *>(target), rom_fetcher);
Adds the IIgs as a user-selectable machine. Albeit that there is no underlying machine yet.
2020-10-21 02:18:11 +00:00
}
Machine::~Machine() {}
Reference in New Issue Copy Permalink