2019-06-29 01:58:38 +00:00
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//
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// TestRunner68000.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 28/06/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef TestRunner68000_h
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#define TestRunner68000_h
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#include <array>
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#include "../../../Processors/68000/68000.hpp"
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using Flag = CPU::MC68000::Flag;
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/*!
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Provides a 68000 with 64kb of RAM in its low address space;
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/RESET will put the supervisor stack pointer at 0xFFFF and
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begin execution at 0x0400.
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*/
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class RAM68000: public CPU::MC68000::BusHandler {
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public:
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RAM68000() : m68000_(*this) {
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// Setup the /RESET vector.
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ram_[0] = 0;
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ram_[1] = 0x206; // Supervisor stack pointer.
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ram_[2] = 0;
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ram_[3] = 0x1000; // Initial PC.
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// Ensure the condition codes start unset.
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auto state = get_processor_state();
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state.status &= ~Flag::ConditionCodes;
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set_processor_state(state);
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}
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void set_program(const std::vector<uint16_t> &program) {
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memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t));
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// Add a NOP suffix, to avoid corrupting flags should the attempt to
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// run for a certain number of instructions overrun.
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ram_[(0x1000 >> 1) + program.size()] = 0x4e71;
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}
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void set_initial_stack_pointer(uint32_t sp) {
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ram_[0] = sp >> 16;
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ram_[1] = sp & 0xffff;
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}
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2020-09-27 19:10:29 +00:00
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void will_perform(uint32_t, uint16_t) {
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2019-06-29 01:58:38 +00:00
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--instructions_remaining_;
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}
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void run_for_instructions(int count) {
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instructions_remaining_ = count + (has_run_ ? 0 : 1);
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finish_reset_if_needed();
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while(instructions_remaining_) {
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run_for(HalfCycles(2));
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}
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}
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void run_for(HalfCycles cycles) {
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finish_reset_if_needed();
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m68000_.run_for(cycles);
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}
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void finish_reset_if_needed() {
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// If the 68000 hasn't run yet, build in the necessary
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// cycles to finish the reset program, and set the stored state.
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if(!has_run_) {
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has_run_ = true;
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m68000_.run_for(HalfCycles(76));
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duration_ -= HalfCycles(76);
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}
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}
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uint16_t *ram_at(uint32_t address) {
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return &ram_[(address >> 1) % ram_.size()];
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}
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2020-09-27 19:10:29 +00:00
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
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2019-06-29 01:58:38 +00:00
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const uint32_t word_address = cycle.word_address();
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if(instructions_remaining_) duration_ += cycle.length;
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using Microcycle = CPU::MC68000::Microcycle;
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if(cycle.data_select_active()) {
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if(cycle.operation & Microcycle::InterruptAcknowledge) {
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cycle.value->halves.low = 10;
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} else {
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = ram_[word_address % ram_.size()];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = ram_[word_address % ram_.size()] >> cycle.byte_shift();
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break;
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case Microcycle::SelectWord:
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ram_[word_address % ram_.size()] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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ram_[word_address % ram_.size()] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(ram_[word_address % ram_.size()] & cycle.untouched_byte_mask())
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);
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break;
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}
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}
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}
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return HalfCycles(0);
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}
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CPU::MC68000::Processor<RAM68000, true>::State get_processor_state() {
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return m68000_.get_state();
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}
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void set_processor_state(const CPU::MC68000::Processor<RAM68000, true>::State &state) {
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m68000_.set_state(state);
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}
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CPU::MC68000::Processor<RAM68000, true, true> &processor() {
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return m68000_;
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}
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int get_cycle_count() {
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2019-10-30 02:36:29 +00:00
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return int(duration_.as_integral()) >> 1;
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2019-06-29 01:58:38 +00:00
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}
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2020-01-09 03:35:28 +00:00
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void reset_cycle_count() {
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duration_ = HalfCycles(0);
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}
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2019-06-29 01:58:38 +00:00
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private:
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CPU::MC68000::Processor<RAM68000, true, true> m68000_;
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2019-07-01 01:43:30 +00:00
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std::array<uint16_t, 256*1024> ram_{};
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2019-06-29 01:58:38 +00:00
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int instructions_remaining_;
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HalfCycles duration_;
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bool has_run_ = false;
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};
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#endif /* TestRunner68000_h */
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