2017-05-17 01:28:17 +00:00
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//
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// AllRAMProcessor.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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2018-05-13 19:19:52 +00:00
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// Copyright 2017 Thomas Harte. All rights reserved.
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2017-05-17 01:28:17 +00:00
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//
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#include "AllRAMProcessor.hpp"
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using namespace CPU;
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2017-11-11 20:28:40 +00:00
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AllRAMProcessor::AllRAMProcessor(std::size_t memory_size) :
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2017-05-17 01:28:17 +00:00
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memory_(memory_size),
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2017-06-04 01:54:42 +00:00
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traps_(memory_size, false),
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2017-05-17 01:28:17 +00:00
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timestamp_(0) {}
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2017-11-11 20:28:40 +00:00
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void AllRAMProcessor::set_data_at_address(uint16_t startAddress, std::size_t length, const uint8_t *data) {
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2020-05-10 03:00:39 +00:00
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std::size_t endAddress = std::min(startAddress + length, size_t(65536));
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2017-11-11 20:28:40 +00:00
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std::memcpy(&memory_[startAddress], data, endAddress - startAddress);
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2017-05-17 01:28:17 +00:00
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}
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2017-11-11 20:28:40 +00:00
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void AllRAMProcessor::get_data_at_address(uint16_t startAddress, std::size_t length, uint8_t *data) {
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2020-05-10 03:00:39 +00:00
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std::size_t endAddress = std::min(startAddress + length, size_t(65536));
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2017-11-11 20:28:40 +00:00
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std::memcpy(data, &memory_[startAddress], endAddress - startAddress);
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2017-05-20 01:53:39 +00:00
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}
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2017-07-28 00:17:13 +00:00
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HalfCycles AllRAMProcessor::get_timestamp() {
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2017-05-17 01:28:17 +00:00
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return timestamp_;
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}
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2017-05-20 01:20:28 +00:00
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void AllRAMProcessor::set_trap_handler(TrapHandler *trap_handler) {
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trap_handler_ = trap_handler;
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}
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void AllRAMProcessor::add_trap_address(uint16_t address) {
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2017-06-04 01:54:42 +00:00
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traps_[address] = true;
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2017-05-20 01:20:28 +00:00
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}
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