2024-02-17 02:35:49 +00:00
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//
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// Decoder.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "Model.hpp"
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#include "Operation.hpp"
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#include <array>
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namespace InstructionSet::ARM {
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template <Model model>
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using OperationTable = std::array<Operation, 256>;
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template <Model model>
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constexpr OperationTable<model> operation_table() {
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OperationTable<model> result{};
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for(std::size_t c = 0; c < result.size(); c++) {
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const auto opcode = static_cast<uint32_t>(c << 20);
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// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case. More specific
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// page references are provided were more detailed versions of the
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// decoding are depicted.
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// Data processing; cf. p.17.
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if(((opcode >> 26) & 0b11) == 0b00) {
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const auto operation = (c >> 21) & 0xf;
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if((opcode >> 20) & 1) {
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result[c] = Operation(int(Operation::ANDS) + operation);
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} else {
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result[c] = Operation(int(Operation::AND) + operation);
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}
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continue;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if(((opcode >> 22) & 0b111'111) == 0b000'000) {
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switch((opcode >> 20) & 3) {
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case 0: result[c] = Operation::MUL; break;
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case 1: result[c] = Operation::MULS; break;
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case 2: result[c] = Operation::MLA; break;
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case 3: result[c] = Operation::MLAS; break;
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}
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continue;
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if(((opcode >> 26) & 0b11) == 0b01) {
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result[c] =
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((opcode >> 20) & 1) ? Operation::LDR : Operation::STR;
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continue;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if(((opcode >> 25) & 0b111) == 0b100) {
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result[c] =
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((opcode >> 20) & 1) ? Operation::LDM : Operation::STM;
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continue;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if(((opcode >> 25) & 0b111) == 0b101) {
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result[c] =
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((opcode >> 24) & 1) ? Operation::BL : Operation::B;
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continue;
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}
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if(((opcode >> 25) & 0b111) == 0b110) {
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result[c] = Operation::CoprocessorDataTransfer;
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continue;
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}
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if(((opcode >> 24) & 0b1111) == 0b1110) {
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result[c] = Operation::CoprocessorDataOperationOrRegisterTransfer;
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continue;
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}
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if(((opcode >> 24) & 0b1111) == 0b1111) {
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result[c] = Operation::SoftwareInterrupt;
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continue;
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}
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result[c] = Operation::Undefined;
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}
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return result;
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}
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template <Model model>
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constexpr Operation operation(uint32_t opcode) {
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constexpr OperationTable<model> operations = operation_table<model>();
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const auto op = operations[(opcode >> 21) & 0x7f];
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// MUL and MLA have an extra constraint that doesn't fit the neat
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// 256-entry table format as above.
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//
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// Hope: most instructions aren't MUL/MLA so relying on the branch predictor
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// here is fine.
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if(
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is_multiply(op)
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&& ((opcode >> 4) & 0b1111) != 0b1001
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) {
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return Operation::Undefined;
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}
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return op;
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}
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}
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