2017-06-04 21:55:19 +00:00
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//
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// ZX8081.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/06/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "ZX8081.hpp"
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2017-06-05 14:36:07 +00:00
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#include "../MemoryFuzzer.hpp"
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2017-06-05 13:38:49 +00:00
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2017-06-04 21:55:19 +00:00
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using namespace ZX8081;
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2017-06-04 22:32:23 +00:00
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Machine::Machine() :
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2017-06-05 01:54:55 +00:00
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vsync_(false),
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hsync_(false),
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2017-06-05 14:47:42 +00:00
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ram_(1024),
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line_data_(nullptr) {
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2017-06-04 21:55:19 +00:00
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// run at 3.25 Mhz
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set_clock_rate(3250000);
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2017-06-05 14:36:07 +00:00
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Memory::Fuzz(ram_);
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2017-06-04 21:55:19 +00:00
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}
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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2017-06-04 22:32:23 +00:00
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cycles_since_display_update_ += cycle.length;
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uint8_t r;
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2017-06-05 13:38:49 +00:00
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uint16_t address = cycle.address ? *cycle.address : 0;
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2017-06-04 22:32:23 +00:00
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switch(cycle.operation) {
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case CPU::Z80::BusOperation::Output:
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2017-06-05 14:36:07 +00:00
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if((address&7) == 7) {
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2017-06-05 01:54:55 +00:00
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set_vsync(false);
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2017-06-04 22:32:23 +00:00
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}
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break;
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case CPU::Z80::BusOperation::Input:
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2017-06-05 14:36:07 +00:00
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if((address&7) == 6) {
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2017-06-05 01:54:55 +00:00
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set_vsync(true);
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2017-06-04 22:32:23 +00:00
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}
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2017-06-05 01:54:55 +00:00
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*cycle.value = 0xff;
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2017-06-04 22:32:23 +00:00
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break;
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case CPU::Z80::BusOperation::Interrupt:
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2017-06-05 01:54:55 +00:00
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set_hsync(true);
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2017-06-04 22:32:23 +00:00
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*cycle.value = 0xff;
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break;
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case CPU::Z80::BusOperation::ReadOpcode:
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2017-06-05 01:54:55 +00:00
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set_hsync(false);
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2017-06-04 22:32:23 +00:00
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r = (uint8_t)get_value_of_register(CPU::Z80::Register::R);
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set_interrupt_line(!(r & 0x40));
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case CPU::Z80::BusOperation::Read:
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2017-06-05 13:38:49 +00:00
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if((address & 0xc000) == 0x0000) *cycle.value = rom_[address & (rom_.size() - 1)];
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else if((address & 0x4000) == 0x4000) {
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uint8_t value = ram_[address & 1023];
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if(address&0x8000 && !(value & 0x40) && cycle.operation == CPU::Z80::BusOperation::ReadOpcode && !get_halt_line()) {
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2017-06-04 22:32:23 +00:00
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// TODO: character lookup.
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output_byte(value);
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*cycle.value = 0;
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2017-06-05 14:36:07 +00:00
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} else *cycle.value = value;
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2017-06-04 22:32:23 +00:00
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}
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break;
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case CPU::Z80::BusOperation::Write:
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2017-06-05 13:38:49 +00:00
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if((address & 0x4000) == 0x4000) ram_[address & 1023] = *cycle.value;
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2017-06-04 22:32:23 +00:00
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break;
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default: break;
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}
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2017-06-04 21:55:19 +00:00
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return 0;
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}
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void Machine::setup_output(float aspect_ratio) {
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2017-06-06 03:32:49 +00:00
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crt_.reset(new Outputs::CRT::CRT(210, 1, Outputs::CRT::DisplayType::PAL50, 1));
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2017-06-04 21:55:19 +00:00
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crt_->set_rgb_sampling_function(
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"vec3 rgb_sample(usampler2D sampler, vec2 coordinate, vec2 icoordinate)"
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"{"
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"return vec3(float(texture(texID, coordinate).r) / 255.0);"
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2017-06-04 21:55:19 +00:00
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"}");
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}
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2017-06-04 22:08:35 +00:00
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void Machine::flush() {
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2017-06-04 22:32:23 +00:00
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update_display();
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2017-06-04 22:08:35 +00:00
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}
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2017-06-04 21:55:19 +00:00
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void Machine::close_output() {
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}
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std::shared_ptr<Outputs::CRT::CRT> Machine::get_crt() {
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return crt_;
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}
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std::shared_ptr<Outputs::Speaker> Machine::get_speaker() {
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return nullptr;
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}
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void Machine::run_for_cycles(int number_of_cycles) {
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2017-06-04 22:37:13 +00:00
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CPU::Z80::Processor<Machine>::run_for_cycles(number_of_cycles);
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2017-06-04 21:55:19 +00:00
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}
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void Machine::configure_as_target(const StaticAnalyser::Target &target) {
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2017-06-04 22:32:23 +00:00
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// TODO: pay attention to the target
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rom_ = zx80_rom_;
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2017-06-04 21:55:19 +00:00
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}
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2017-06-04 22:08:35 +00:00
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void Machine::set_rom(ROMType type, std::vector<uint8_t> data) {
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switch(type) {
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case ZX80: zx80_rom_ = data; break;
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case ZX81: zx81_rom_ = data; break;
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}
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}
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2017-06-04 22:32:23 +00:00
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#pragma mark - Video
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void Machine::update_display() {
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2017-06-05 14:47:42 +00:00
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// cycles_since_display_update_ = 0;
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2017-06-04 22:32:23 +00:00
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}
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2017-06-05 01:54:55 +00:00
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void Machine::set_vsync(bool sync) {
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2017-06-05 13:38:49 +00:00
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if(sync == vsync_) return;
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2017-06-05 01:54:55 +00:00
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vsync_ = sync;
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2017-06-05 14:47:42 +00:00
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update_sync();
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2017-06-05 01:54:55 +00:00
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}
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void Machine::set_hsync(bool sync) {
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2017-06-05 13:38:49 +00:00
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if(sync == hsync_) return;
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2017-06-05 01:54:55 +00:00
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hsync_ = sync;
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2017-06-05 14:47:42 +00:00
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update_sync();
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}
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void Machine::update_sync() {
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bool is_sync = hsync_ || vsync_;
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if(is_sync == is_sync_) return;
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2017-06-06 03:32:49 +00:00
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if(line_data_) {
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output_data();
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}
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2017-06-05 14:47:42 +00:00
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if(is_sync_) {
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crt_->output_sync(cycles_since_display_update_);
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} else {
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output_level(cycles_since_display_update_);
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}
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cycles_since_display_update_ = 0;
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is_sync_ = is_sync;
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}
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void Machine::output_level(unsigned int number_of_cycles) {
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uint8_t *colour_pointer = (uint8_t *)crt_->allocate_write_area(1);
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2017-06-06 03:50:04 +00:00
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if(colour_pointer) *colour_pointer = 0xff;
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2017-06-05 14:47:42 +00:00
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crt_->output_level(number_of_cycles);
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2017-06-04 22:32:23 +00:00
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}
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2017-06-06 03:32:49 +00:00
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void Machine::output_data() {
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2017-06-06 03:50:04 +00:00
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unsigned int data_length = (unsigned int)(line_data_pointer_ - line_data_);
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crt_->output_data(data_length, 1);
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2017-06-06 03:32:49 +00:00
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line_data_pointer_ = line_data_ = nullptr;
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cycles_since_display_update_ -= data_length;
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}
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2017-06-04 22:32:23 +00:00
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void Machine::output_byte(uint8_t byte) {
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2017-06-06 03:32:49 +00:00
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if(line_data_) {
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if(cycles_since_display_update_ > 4) {
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output_data();
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}
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2017-06-06 03:50:04 +00:00
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} else {
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output_level(cycles_since_display_update_);
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2017-06-06 03:32:49 +00:00
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}
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2017-06-05 14:47:42 +00:00
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if(!line_data_) {
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2017-06-06 03:32:49 +00:00
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line_data_pointer_ = line_data_ = crt_->allocate_write_area(320);
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}
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if(line_data_) {
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line_data_pointer_[0] = byte;
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line_data_pointer_[1] = byte;
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line_data_pointer_[2] = byte;
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line_data_pointer_[3] = byte;
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line_data_pointer_ += 4;
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2017-06-05 14:47:42 +00:00
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}
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2017-06-04 22:32:23 +00:00
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}
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