2022-05-16 15:44:16 +00:00
|
|
|
//
|
|
|
|
// 68000Mk2Implementation.hpp
|
|
|
|
// Clock Signal
|
|
|
|
//
|
|
|
|
// Created by Thomas Harte on 16/05/2022.
|
|
|
|
// Copyright © 2022 Thomas Harte. All rights reserved.
|
|
|
|
//
|
|
|
|
|
|
|
|
#ifndef _8000Mk2Implementation_h
|
|
|
|
#define _8000Mk2Implementation_h
|
|
|
|
|
2022-05-16 20:57:40 +00:00
|
|
|
#include <cassert>
|
2022-05-17 18:08:50 +00:00
|
|
|
#include <cstdio>
|
2022-05-16 20:57:40 +00:00
|
|
|
|
2022-05-16 15:44:16 +00:00
|
|
|
namespace CPU {
|
|
|
|
namespace MC68000Mk2 {
|
|
|
|
|
2022-05-17 19:05:11 +00:00
|
|
|
// MARK: - The state machine.
|
|
|
|
|
2022-05-16 15:59:03 +00:00
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
|
|
|
void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::run_for(HalfCycles duration) {
|
|
|
|
// Accumulate the newly paid-in cycles. If this instance remains in deficit, exit.
|
2022-05-16 20:57:40 +00:00
|
|
|
time_remaining_ += duration;
|
|
|
|
if(time_remaining_ <= HalfCycles(0)) return;
|
2022-05-16 15:59:03 +00:00
|
|
|
|
|
|
|
// Check whether all remaining time has been expended; if so then exit, having set this line up as
|
|
|
|
// the next resumption point.
|
2022-05-17 00:38:17 +00:00
|
|
|
#define ConsiderExit() if(time_remaining_ <= HalfCycles(0)) { state_ = __COUNTER__+1; return; } [[fallthrough]]; case __COUNTER__:
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-16 20:57:40 +00:00
|
|
|
// Subtracts `n` half-cycles from `time_remaining_`; if permit_overrun is false, also ConsiderExit()
|
|
|
|
#define Spend(n) time_remaining_ -= (n); if constexpr (!permit_overrun) ConsiderExit()
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-17 01:00:25 +00:00
|
|
|
// Performs ConsiderExit() only if permit_overrun is true.
|
2022-05-16 15:59:03 +00:00
|
|
|
#define CheckOverrun() if constexpr (permit_overrun) ConsiderExit()
|
|
|
|
|
2022-05-17 01:00:25 +00:00
|
|
|
// Sets `x` as the next state, and exits now if all remaining time has been extended and permit_overrun is true.
|
2022-05-17 18:51:49 +00:00
|
|
|
#define MoveToState(x) state_ = (x); if (permit_overrun && time_remaining_ <= HalfCycles(0)) return
|
2022-05-17 01:00:25 +00:00
|
|
|
|
2022-05-16 15:59:03 +00:00
|
|
|
//
|
2022-05-16 20:57:40 +00:00
|
|
|
// So basic structure is, in general:
|
2022-05-16 15:59:03 +00:00
|
|
|
//
|
|
|
|
// case Action:
|
|
|
|
// do_something();
|
|
|
|
// Spend(20);
|
|
|
|
// do_something_else();
|
|
|
|
// Spend(10);
|
|
|
|
// do_a_third_thing();
|
|
|
|
// Spend(30);
|
|
|
|
//
|
2022-05-17 01:00:25 +00:00
|
|
|
// MoveToState(next_action);
|
2022-05-16 15:59:03 +00:00
|
|
|
// break;
|
|
|
|
//
|
|
|
|
// Additional notes:
|
|
|
|
//
|
|
|
|
// Action and all equivalents should be negative values, since the
|
2022-05-17 00:38:17 +00:00
|
|
|
// switch-for-computed-goto-for-a-coroutine structure uses __COUNTER__* for
|
2022-05-16 15:59:03 +00:00
|
|
|
// its invented entry- and exit-points, meaning that negative numbers are
|
|
|
|
// the easiest group that is safely definitely never going to collide.
|
2022-05-17 00:38:17 +00:00
|
|
|
//
|
|
|
|
// (* an extension supported by at least GCC, Clang and MSVC)
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
// Spare containers:
|
2022-05-17 00:38:17 +00:00
|
|
|
HalfCycles delay; // To receive any additional time added on by calls to perform_bus_operation.
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
// Helper macros for common bus transactions:
|
|
|
|
|
|
|
|
// Performs the bus operation and then applies a `Spend` of its length
|
|
|
|
// plus any additional length returned by the bus handler.
|
|
|
|
#define PerformBusOperation(x) \
|
|
|
|
delay = bus_handler_.perform_bus_operation(x, is_supervisor_); \
|
|
|
|
Spend(x.length + delay)
|
|
|
|
|
|
|
|
// Performs no bus activity for the specified number of microcycles.
|
|
|
|
#define IdleBus(n) \
|
|
|
|
idle.length = HalfCycles(n * 4); \
|
|
|
|
PerformBusOperation(idle)
|
|
|
|
|
|
|
|
// Spin until DTACK, VPA or BERR is asserted (unless DTACK is implicit),
|
|
|
|
// holding the bus cycle provided.
|
|
|
|
#define WaitForDTACK(x) \
|
|
|
|
if constexpr (!dtack_is_implicit && !dtack_ && !vpa_ && !berr_) { \
|
|
|
|
awaiting_dtack = x; \
|
|
|
|
awaiting_dtack.length = HalfCycles(2); \
|
2022-05-17 00:38:17 +00:00
|
|
|
post_dtack_state_ = __COUNTER__+1; \
|
2022-05-16 20:57:40 +00:00
|
|
|
state_ = State::WaitForDTACK; \
|
|
|
|
break; \
|
|
|
|
} \
|
2022-05-17 00:38:17 +00:00
|
|
|
[[fallthrough]]; case __COUNTER__:
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
// Performs the bus operation provided, which will be one with a
|
|
|
|
// SelectWord or SelectByte operation, stretching it to match the E
|
|
|
|
// bus if VPA is currently asserted.
|
|
|
|
//
|
|
|
|
// TODO: If BERR is asserted, stop here and perform a bus error exception.
|
|
|
|
//
|
|
|
|
// TODO: If VPA is asserted, stretch this cycle.
|
|
|
|
#define CompleteAccess(x) \
|
|
|
|
PerformBusOperation(x)
|
|
|
|
|
|
|
|
// Performs the memory access implied by the announce, perform pair,
|
|
|
|
// honouring DTACK, BERR and VPA as necessary.
|
|
|
|
#define AccessPair(addr, val, announce, perform) \
|
2022-05-17 20:10:20 +00:00
|
|
|
announce.address = perform.address = &addr; \
|
2022-05-16 20:57:40 +00:00
|
|
|
perform.value = &val; \
|
|
|
|
if constexpr (!dtack_is_implicit) { \
|
|
|
|
announce.length = HalfCycles(4); \
|
|
|
|
} \
|
|
|
|
PerformBusOperation(announce); \
|
|
|
|
WaitForDTACK(announce); \
|
|
|
|
CompleteAccess(perform);
|
|
|
|
|
|
|
|
// Reads the data (i.e. non-program) word from addr into val.
|
2022-05-17 20:10:20 +00:00
|
|
|
#define ReadDataWord(addr, val) \
|
|
|
|
AccessPair(addr, val, read_word_data_announce, read_word_data)
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
// Reads the program (i.e. non-data) word from addr into val.
|
2022-05-17 20:10:20 +00:00
|
|
|
#define ReadProgramWord(val) \
|
2022-05-16 20:57:40 +00:00
|
|
|
AccessPair(program_counter_.l, val, read_program_announce, read_program); \
|
|
|
|
program_counter_.l += 2;
|
|
|
|
|
|
|
|
// Reads one futher word from the program counter and inserts it into
|
|
|
|
// the prefetch queue.
|
|
|
|
#define Prefetch() \
|
2022-05-17 12:26:35 +00:00
|
|
|
prefetch_.high = prefetch_.low; \
|
|
|
|
ReadProgramWord(prefetch_.low)
|
2022-05-16 20:57:40 +00:00
|
|
|
|
2022-05-17 18:08:50 +00:00
|
|
|
using Mode = InstructionSet::M68k::AddressingMode;
|
|
|
|
|
2022-05-16 15:59:03 +00:00
|
|
|
// Otherwise continue for all time, until back in debt.
|
|
|
|
// Formatting is slightly obtuse here to make this look more like a coroutine.
|
2022-05-16 20:57:40 +00:00
|
|
|
while(true) { switch(state_) {
|
|
|
|
|
|
|
|
// Spin in place, one cycle at a time, until one of DTACK,
|
|
|
|
// BERR or VPA is asserted.
|
|
|
|
case State::WaitForDTACK:
|
|
|
|
PerformBusOperation(awaiting_dtack);
|
|
|
|
|
|
|
|
if(dtack_ || berr_ || vpa_) {
|
|
|
|
state_ = post_dtack_state_;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Perform the RESET exception, which seeds the stack pointer and program
|
|
|
|
// counter, populates the prefetch queue, and then moves to instruction dispatch.
|
|
|
|
case State::Reset:
|
|
|
|
IdleBus(7); // (n-)*5 nn
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
// Establish general reset state.
|
|
|
|
status_.is_supervisor = true;
|
|
|
|
status_.interrupt_level = 7;
|
|
|
|
status_.trace_flag = 0;
|
|
|
|
did_update_status();
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
temporary_address_ = 0;
|
|
|
|
ReadDataWord(temporary_address_, registers_[15].high); // nF
|
|
|
|
|
|
|
|
temporary_address_ += 2;
|
|
|
|
ReadDataWord(temporary_address_, registers_[15].low); // nf
|
|
|
|
|
|
|
|
temporary_address_ += 2;
|
|
|
|
ReadDataWord(temporary_address_, program_counter_.high); // nV
|
|
|
|
|
|
|
|
temporary_address_ += 2;
|
|
|
|
ReadDataWord(temporary_address_, program_counter_.low); // nv
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-17 12:26:35 +00:00
|
|
|
MoveToState(State::Decode);
|
2022-05-16 20:57:40 +00:00
|
|
|
break;
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-17 12:26:35 +00:00
|
|
|
// Inspect the prefetch queue in order to decode the next instruction,
|
|
|
|
// and segue into the fetching of operands.
|
|
|
|
case State::Decode:
|
|
|
|
opcode_ = prefetch_.high.w;
|
|
|
|
instruction_ = decoder_.decode(opcode_);
|
2022-05-17 18:08:50 +00:00
|
|
|
instruction_address_ = program_counter_.l - 4;
|
|
|
|
|
|
|
|
// TODO: check for privilege and unrecognised instructions.
|
2022-05-17 12:26:35 +00:00
|
|
|
|
2022-05-17 19:05:11 +00:00
|
|
|
// Signal the bus handler if requested.
|
|
|
|
if constexpr (signal_will_perform) {
|
|
|
|
bus_handler_.will_perform(instruction_address_, opcode_);
|
|
|
|
}
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
// Obtain operand flags and pick a perform pattern.
|
|
|
|
setup_operation();
|
|
|
|
|
2022-05-17 19:05:11 +00:00
|
|
|
// Ensure the first parameter is next fetched.
|
2022-05-17 18:08:50 +00:00
|
|
|
next_operand_ = 0;
|
2022-05-17 12:26:35 +00:00
|
|
|
[[fallthrough]];
|
|
|
|
|
|
|
|
// Check the operand flags to determine whether the operand at index
|
2022-05-17 18:51:49 +00:00
|
|
|
// operand_ needs to be fetched, and if so then calculate the EA and
|
|
|
|
// do so.
|
|
|
|
//
|
|
|
|
// Per Yacht, all instructions other than MOVE.[b/w/;] will read all
|
|
|
|
// relevant operands — even when that's a useless endeavour, such as
|
|
|
|
// for CLR or MOVE SR, <ea>.
|
|
|
|
//
|
|
|
|
// TODO: add MOVE special case, somewhere.
|
2022-05-17 12:26:35 +00:00
|
|
|
case State::FetchOperand:
|
2022-05-17 20:57:33 +00:00
|
|
|
// Check that this operand is meant to be fetched.
|
|
|
|
if(!(operand_flags_ & (1 << next_operand_))) {
|
|
|
|
state_ = perform_state_;
|
2022-05-17 18:08:50 +00:00
|
|
|
continue;
|
2022-05-17 20:57:33 +00:00
|
|
|
}
|
2022-05-17 18:08:50 +00:00
|
|
|
|
2022-05-17 20:57:33 +00:00
|
|
|
// Figure out how to fetch it.
|
|
|
|
switch(instruction_.mode(next_operand_)) {
|
2022-05-17 18:08:50 +00:00
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
|
|
|
|
++next_operand_;
|
2022-05-17 18:51:49 +00:00
|
|
|
state_ = next_operand_ == 2 ? perform_state_ : State::FetchOperand;
|
2022-05-17 18:08:50 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
}
|
2022-05-17 18:51:49 +00:00
|
|
|
break;
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
// Store operand is a lot simpler: only one operand is ever stored, and its address
|
|
|
|
// is already known. So this can either skip straight back to ::Decode if the target
|
|
|
|
// is a register, otherwise a single write operation can occur.
|
|
|
|
case State::StoreOperand:
|
|
|
|
if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
|
|
|
|
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
|
|
|
|
state_ = State::Decode;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// TODO: make a decision on how I'm going to deal with byte/word/longword.
|
|
|
|
assert(false);
|
|
|
|
break;
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
//
|
|
|
|
// Various forms of perform.
|
|
|
|
//
|
2022-05-17 20:10:20 +00:00
|
|
|
#define MoveToWritePhase() \
|
|
|
|
next_operand_ = operand_flags_ >> 3; \
|
|
|
|
MoveToState(operand_flags_ & 0x0c ? State::StoreOperand : State::Decode)
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
case State::Perform_np:
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
Prefetch(); // np
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
MoveToWritePhase();
|
2022-05-17 18:51:49 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case State::Perform_np_n:
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(1); // n
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
MoveToWritePhase();
|
2022-05-17 18:51:49 +00:00
|
|
|
break;
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
#undef MoveToWritePhase
|
2022-05-17 12:26:35 +00:00
|
|
|
|
2022-05-17 01:00:25 +00:00
|
|
|
default:
|
2022-05-17 18:51:49 +00:00
|
|
|
printf("Unhandled state: %d\n", state_);
|
2022-05-17 01:00:25 +00:00
|
|
|
assert(false);
|
2022-05-16 15:59:03 +00:00
|
|
|
}}
|
|
|
|
|
2022-05-17 01:02:25 +00:00
|
|
|
#undef Prefetch
|
|
|
|
#undef ReadProgramWord
|
|
|
|
#undef ReadDataWord
|
|
|
|
#undef AccessPair
|
|
|
|
#undef CompleteAccess
|
|
|
|
#undef WaitForDTACK
|
|
|
|
#undef IdleBus
|
|
|
|
#undef PerformBusOperation
|
|
|
|
#undef MoveToState
|
2022-05-16 15:59:03 +00:00
|
|
|
#undef CheckOverrun
|
|
|
|
#undef Spend
|
|
|
|
#undef ConsiderExit
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2022-05-17 19:05:11 +00:00
|
|
|
// MARK: - Operation specifications.
|
|
|
|
|
2022-05-17 18:08:50 +00:00
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
|
|
|
void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::setup_operation() {
|
|
|
|
|
|
|
|
#define BIND(x, p) \
|
|
|
|
case InstructionSet::M68k::Operation::x: \
|
|
|
|
operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>(); \
|
2022-05-17 18:51:49 +00:00
|
|
|
perform_state_ = p; \
|
2022-05-17 18:08:50 +00:00
|
|
|
break;
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
using Mode = InstructionSet::M68k::AddressingMode;
|
|
|
|
|
2022-05-17 18:08:50 +00:00
|
|
|
switch(instruction_.operation) {
|
2022-05-17 18:51:49 +00:00
|
|
|
BIND(NBCD, instruction_.mode(0) == Mode::DataRegisterDirect ? State::Perform_np_n : State::Perform_np);
|
2022-05-17 18:08:50 +00:00
|
|
|
|
2022-05-17 20:57:33 +00:00
|
|
|
// MOVEs are a special case for having an operand they write but did not read. So they segue into a
|
|
|
|
// specialised state for writing the result.
|
|
|
|
BIND(MOVEw, State::MOVEWrite);
|
|
|
|
|
2022-05-17 18:08:50 +00:00
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef BIND
|
|
|
|
}
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
// MARK: - Flow Controller.
|
|
|
|
|
|
|
|
void ProcessorBase::did_update_status() {
|
|
|
|
// Shuffle the stack pointers.
|
2022-05-17 20:51:26 +00:00
|
|
|
stack_pointers_[is_supervisor_] = registers_[15];
|
|
|
|
registers_[15] = stack_pointers_[int(status_.is_supervisor)];
|
2022-05-17 18:51:49 +00:00
|
|
|
is_supervisor_ = int(status_.is_supervisor);
|
|
|
|
}
|
|
|
|
|
|
|
|
// MARK: - External state.
|
|
|
|
|
2022-05-17 00:04:13 +00:00
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
|
|
|
CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::get_state() {
|
2022-05-17 20:51:26 +00:00
|
|
|
CPU::MC68000Mk2::State state;
|
|
|
|
|
|
|
|
// This isn't true, but will ensure that both stack_pointers_ have their proper values.
|
|
|
|
did_update_status();
|
|
|
|
|
|
|
|
for(int c = 0; c < 7; c++) {
|
|
|
|
state.registers.data[c] = registers_[c].l;
|
|
|
|
state.registers.address[c] = registers_[c + 8].l;
|
|
|
|
}
|
|
|
|
state.registers.data[7] = registers_[7].l;
|
|
|
|
|
|
|
|
state.registers.program_counter = program_counter_.l;
|
|
|
|
state.registers.status = status_.status();
|
|
|
|
state.registers.user_stack_pointer = stack_pointers_[0].l;
|
|
|
|
state.registers.supervisor_stack_pointer = stack_pointers_[1].l;
|
|
|
|
|
|
|
|
return state;
|
2022-05-17 00:04:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
2022-05-17 20:51:26 +00:00
|
|
|
void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::set_state(const CPU::MC68000Mk2::State &state) {
|
|
|
|
// Copy registers and the program counter.
|
|
|
|
for(int c = 0; c < 7; c++) {
|
|
|
|
registers_[c].l = state.registers.data[c];
|
|
|
|
registers_[c + 8].l = state.registers.address[c];
|
|
|
|
}
|
|
|
|
registers_[7].l = state.registers.data[7];
|
|
|
|
program_counter_.l = state.registers.program_counter;
|
|
|
|
|
|
|
|
// Set status first in order to get the proper is-supervisor flag in place.
|
|
|
|
status_.set_status(state.registers.status);
|
|
|
|
|
|
|
|
// Update stack pointers, being careful to copy the right one.
|
|
|
|
stack_pointers_[0].l = state.registers.user_stack_pointer;
|
|
|
|
stack_pointers_[1].l = state.registers.supervisor_stack_pointer;
|
|
|
|
registers_[15] = stack_pointers_[is_supervisor_];
|
|
|
|
|
|
|
|
// Ensure the local is-supervisor flag is updated.
|
|
|
|
did_update_status();
|
2022-05-17 00:04:13 +00:00
|
|
|
}
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
|
2022-05-16 15:44:16 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* _8000Mk2Implementation_h */
|