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https://github.com/TomHarte/CLK.git
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146 lines
4.7 KiB
C++
146 lines
4.7 KiB
C++
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//
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// InstructionOperandFlags.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 09/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_InstructionOperandFlags_hpp
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#define InstructionSets_68k_InstructionOperandFlags_hpp
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namespace InstructionSet {
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namespace M68k {
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template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_operation) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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// (which means that source and destination will appear as their effective addresses)
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//
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case Operation::PEA:
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case Operation::JMP: case Operation::JSR:
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case Operation::MOVEPw: case Operation::MOVEPl:
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case Operation::MOVEMtoMw: case Operation::MOVEMtoMl:
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case Operation::MOVEMtoRw: case Operation::MOVEMtoRl:
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case Operation::TAS:
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case Operation::RTR: case Operation::RTS: case Operation::RTE:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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case Operation::Bccb: case Operation::Bccw: case Operation::Bccl:
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case Operation::BSRb: case Operation::BSRw: case Operation::BSRl:
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case Operation::TSTb: case Operation::TSTw: case Operation::TSTl:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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case Operation::Scc:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::NOTb: case Operation::NOTw: case Operation::NOTl:
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case Operation::NEGb: case Operation::NEGw: case Operation::NEGl:
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case Operation::NEGXb: case Operation::NEGXw: case Operation::NEGXl:
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case Operation::EXTbtow: case Operation::EXTwtol:
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case Operation::SWAP:
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case Operation::UNLINK:
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case Operation::ASLm: case Operation::ASRm:
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case Operation::LSLm: case Operation::LSRm:
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case Operation::ROLm: case Operation::RORm:
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case Operation::ROXLm: case Operation::ROXRm:
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return FetchOp1 | StoreOp1;
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//
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// CLR, which is model-dependent.
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//
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case Operation::CLRb: case Operation::CLRw: case Operation::CLRl:
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if constexpr (model == Model::M68000) {
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return FetchOp1 | StoreOp1;
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} else {
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return StoreOp1;
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}
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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case Operation::CHK:
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case Operation::BTST:
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case Operation::LINKw:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::ASLb: case Operation::ASLw: case Operation::ASLl:
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case Operation::ASRb: case Operation::ASRw: case Operation::ASRl:
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case Operation::LSLb: case Operation::LSLw: case Operation::LSLl:
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case Operation::LSRb: case Operation::LSRw: case Operation::LSRl:
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case Operation::ROLb: case Operation::ROLw: case Operation::ROLl:
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case Operation::RORb: case Operation::RORw: case Operation::RORl:
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case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
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case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl:
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case Operation::BCHG:
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case Operation::BCLR: case Operation::BSET:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write source.
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//
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case Operation::DBcc:
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return FetchOp1 | FetchOp2 | StoreOp1;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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//
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// Two-operand; just write destination.
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//
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case Operation::LEA:
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return StoreOp2;
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}
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}
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}
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}
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#endif /* InstructionSets_68k_InstructionOperandFlags_hpp */
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