2019-03-10 21:27:34 +00:00
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//
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// 68000Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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2019-03-24 22:20:54 +00:00
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#define get_status() \
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( \
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(carry_flag_ ? 0x0001 : 0x0000) | \
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(overflow_flag_ ? 0x0002 : 0x0000) | \
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(zero_result_ ? 0x0000 : 0x0004) | \
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(negative_flag_ ? 0x0008 : 0x0000) | \
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(extend_flag_ ? 0x0010 : 0x0000) | \
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(interrupt_level_ << 8) | \
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(trace_flag_ ? 0x8000 : 0x0000) | \
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(is_supervisor_ << 13) \
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)
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#define set_status(x) \
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carry_flag_ = (x) & 0x0001; \
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overflow_flag_ = (x) & 0x0002; \
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zero_result_ = ((x) & 0x0004) ^ 0x0004; \
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negative_flag_ = (x) & 0x0008; \
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extend_flag_ = (x) & 0x0010; \
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interrupt_level_ = ((x) >> 8) & 7; \
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trace_flag_ = (x) & 0x8000; \
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is_supervisor_ = ((x) >> 13) & 1;
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2019-03-10 22:40:12 +00:00
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template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::run_for(HalfCycles duration) {
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2019-03-22 02:30:41 +00:00
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HalfCycles remaining_duration = duration + half_cycles_left_to_run_;
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while(remaining_duration > HalfCycles(0)) {
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2019-03-17 03:01:56 +00:00
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/*
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2019-03-22 02:30:41 +00:00
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FIND THE NEXT MICRO-OP IF UNKNOWN.
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2019-03-17 03:01:56 +00:00
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*/
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2019-03-22 02:30:41 +00:00
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if(active_step_->is_terminal()) {
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while(true) {
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// If there are any more micro-operations available, just move onwards.
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if(active_micro_op_ && !active_micro_op_->is_terminal()) {
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++active_micro_op_;
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} else {
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// Either the micro-operations for this instruction have been exhausted, or
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// no instruction was ongoing. Either way, do a standard instruction operation.
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// TODO: unless an interrupt is pending, or the trap flag is set.
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const uint16_t next_instruction = prefetch_queue_.halves.high.full;
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if(!instructions[next_instruction].micro_operations) {
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// TODO: once all instructions are implemnted, this should be an instruction error.
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std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << next_instruction << std::endl;
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return;
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2019-03-30 03:13:41 +00:00
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} else {
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std::cout << "Performing " << std::hex << next_instruction << std::endl;
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2019-03-19 02:51:32 +00:00
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}
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2019-03-17 18:34:16 +00:00
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2019-03-22 02:30:41 +00:00
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active_program_ = &instructions[next_instruction];
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active_micro_op_ = active_program_->micro_operations;
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}
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2019-03-19 02:51:32 +00:00
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2019-03-22 02:30:41 +00:00
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switch(active_micro_op_->action) {
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default:
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std::cerr << "Unhandled 68000 micro op action " << std::hex << active_micro_op_->action << std::endl;
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break;
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case int(MicroOp::Action::None): break;
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case int(MicroOp::Action::PerformOperation):
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switch(active_program_->operation) {
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2019-03-25 03:05:57 +00:00
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/*
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ABCD adds the lowest bytes form the source and destination using BCD arithmetic,
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obeying the extend flag.
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*/
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2019-03-22 02:30:41 +00:00
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case Operation::ABCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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// Perform the BCD add by evaluating the two nibbles separately.
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int result = (destination & 0xf) + (source & 0xf) + (extend_flag_ ? 1 : 0);
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if(result > 0x09) result += 0x06;
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result += (destination & 0xf0) + (source & 0xf0);
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if(result > 0x99) result += 0x60;
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// Set all flags essentially as if this were normal addition.
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2019-03-24 22:20:54 +00:00
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zero_result_ |= result & 0xff;
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2019-03-22 02:30:41 +00:00
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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overflow_flag_ = ~(source ^ destination) & (destination ^ result) & 0x80;
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// Store the result.
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active_program_->destination->halves.low.halves.low = uint8_t(result);
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} break;
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2019-03-26 02:54:49 +00:00
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// BRA: alters the program counter, exclusively via the prefetch queue.
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case Operation::BRA: {
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const int8_t byte_offset = int8_t(prefetch_queue_.halves.high.halves.low);
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// A non-zero offset byte branches by just that amount; otherwise use the word
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// after as an offset. In both cases, treat as signed.
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if(byte_offset) {
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program_counter_.full = (program_counter_.full + byte_offset) - 2;
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} else {
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program_counter_.full += int16_t(prefetch_queue_.halves.low.full);
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}
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} break;
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// Bcc: evaluates the relevant condition and displacement size and then:
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// if condition is false, schedules bus operations to get past this instruction;
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// otherwise applies the offset and schedules bus operations to refill the prefetch queue.
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case Operation::Bcc: {
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// Grab the 8-bit offset.
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const int8_t byte_offset = int8_t(prefetch_queue_.halves.high.halves.low);
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// Test the conditional.
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bool should_branch;
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switch(prefetch_queue_.halves.high.halves.high & 0xf) {
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default:
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case 0x00: should_branch = true; break; // true
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case 0x01: should_branch = false; break; // false
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case 0x02: should_branch = zero_result_ && !carry_flag_; break; // high
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case 0x03: should_branch = !zero_result_ || carry_flag_; break; // low or same
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case 0x04: should_branch = !carry_flag_; break; // carry clear
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case 0x05: should_branch = carry_flag_; break; // carry set
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case 0x06: should_branch = zero_result_; break; // not equal
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case 0x07: should_branch = !zero_result_; break; // equal
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case 0x08: should_branch = !overflow_flag_; break; // overflow clear
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case 0x09: should_branch = overflow_flag_; break; // overflow set
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case 0x0a: should_branch = !negative_flag_; break; // positive
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case 0x0b: should_branch = negative_flag_; break; // negative
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case 0x0c:
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should_branch = (negative_flag_ && overflow_flag_) || (!negative_flag_ && !overflow_flag_);
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break; // greater than or equal
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case 0x0d:
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should_branch = (negative_flag_ || !overflow_flag_) && (!negative_flag_ || overflow_flag_);
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break; // less than
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case 0x0e:
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should_branch = zero_result_ && ((negative_flag_ && overflow_flag_) || (!negative_flag_ && !overflow_flag_));
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break; // greater than
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case 0x0f:
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should_branch = (!zero_result_ || negative_flag_) && (!overflow_flag_ || !negative_flag_) && overflow_flag_;
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break; // less than or equal
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}
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// Schedule something appropriate, by rewriting the program for this instruction temporarily.
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if(should_branch) {
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if(byte_offset) {
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program_counter_.full = (program_counter_.full + byte_offset) - 2; // - 2 because this should be calculated from the high word of the prefetch.
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} else {
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program_counter_.full += int16_t(prefetch_queue_.halves.low.full);
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}
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active_micro_op_->bus_program = branch_taken_bus_steps_;
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} else {
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if(byte_offset) {
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active_micro_op_->bus_program = branch_byte_not_taken_bus_steps_;
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} else {
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active_micro_op_->bus_program = branch_word_not_taken_bus_steps_;
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}
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}
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} break;
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2019-03-25 03:05:57 +00:00
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/*
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CMP.b, CMP.l and CMP.w: sets the condition flags (other than extend) based on a subtraction
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of the source from the destination; the result of the subtraction is not stored.
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*/
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case Operation::CMPb: {
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2019-03-22 02:30:41 +00:00
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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2019-03-25 03:05:57 +00:00
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const int result = destination - source;
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2019-03-22 02:30:41 +00:00
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2019-03-25 03:05:57 +00:00
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zero_result_ = result & 0xff;
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carry_flag_ = result & ~0xff;
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2019-03-22 02:30:41 +00:00
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negative_flag_ = result & 0x80;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80;
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2019-03-25 03:05:57 +00:00
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} break;
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2019-03-22 02:30:41 +00:00
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2019-03-25 03:05:57 +00:00
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case Operation::CMPw: {
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const uint16_t source = active_program_->source->halves.low.full;
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const uint16_t destination = active_program_->destination->halves.low.full;
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const int result = destination - source;
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zero_result_ = result & 0xffff;
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carry_flag_ = result & ~0xffff;
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negative_flag_ = result & 0x8000;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x8000;
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} break;
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case Operation::CMPl: {
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const uint32_t source = active_program_->source->full;
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const uint32_t destination = active_program_->destination->full;
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const uint64_t result = destination - source;
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zero_result_ = uint32_t(result);
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carry_flag_ = result >> 32;
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negative_flag_ = result & 0x80000000;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80000000;
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2019-03-22 02:30:41 +00:00
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} break;
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2019-04-01 01:13:26 +00:00
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// JMP: copies the source to the program counter.
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case Operation::JMP:
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program_counter_.full = active_program_->source->full;
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break;
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2019-03-22 23:25:53 +00:00
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/*
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MOVE.b, MOVE.l and MOVE.w: move the least significant byte or word, or the entire long word,
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and set negative, zero, overflow and carry as appropriate.
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*/
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2019-03-22 02:30:41 +00:00
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case Operation::MOVEb:
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2019-03-24 22:20:54 +00:00
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zero_result_ = active_program_->destination->halves.low.halves.low = active_program_->source->halves.low.halves.low;
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negative_flag_ = zero_result_ & 0x80;
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2019-03-22 02:30:41 +00:00
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overflow_flag_ = carry_flag_ = 0;
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break;
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case Operation::MOVEw:
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2019-03-24 22:20:54 +00:00
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zero_result_ = active_program_->destination->halves.low.full = active_program_->source->halves.low.full;
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negative_flag_ = zero_result_ & 0x8000;
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2019-03-22 02:30:41 +00:00
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overflow_flag_ = carry_flag_ = 0;
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break;
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case Operation::MOVEl:
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2019-03-24 22:20:54 +00:00
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zero_result_ = active_program_->destination->full = active_program_->source->full;
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negative_flag_ = zero_result_ & 0x80000000;
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2019-03-22 02:30:41 +00:00
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overflow_flag_ = carry_flag_ = 0;
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break;
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2019-03-30 03:13:41 +00:00
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/*
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MOVE.q: a single byte is moved from the current instruction, and sign extended.
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*/
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case Operation::MOVEq:
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zero_result_ = active_program_->destination->full = prefetch_queue_.halves.high.halves.low;
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negative_flag_ = zero_result_ & 0x80;
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overflow_flag_ = carry_flag_ = 0;
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active_program_->destination->full |= negative_flag_ ? 0xffffff00 : 0;
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break;
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2019-03-22 23:25:53 +00:00
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/*
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MOVEA.l: move the entire long word;
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MOVEA.w: move the least significant word and sign extend it.
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Neither sets any flags.
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*/
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case Operation::MOVEAw:
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active_program_->destination->halves.low.full = active_program_->source->halves.low.full;
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active_program_->destination->halves.high.full = (active_program_->destination->halves.low.full & 0x8000) ? 0xffff : 0;
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break;
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case Operation::MOVEAl:
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active_program_->destination->full = active_program_->source->full;
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break;
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2019-03-24 22:20:54 +00:00
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/*
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Status word moves.
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*/
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case Operation::MOVEtoSR:
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set_status(active_program_->source->full);
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break;
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case Operation::MOVEfromSR:
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active_program_->source->halves.low.full = get_status();
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break;
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2019-03-30 03:40:54 +00:00
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/*
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The no-op.
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*/
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case Operation::None:
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break;
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2019-03-25 03:05:57 +00:00
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/*
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SBCD subtracts the lowest byte of the source from that of the destination using
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BCD arithmetic, obeying the extend flag.
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*/
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case Operation::SBCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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// Perform the BCD add by evaluating the two nibbles separately.
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int result = (destination & 0xf) - (source & 0xf) - (extend_flag_ ? 1 : 0);
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if(result > 0x09) result -= 0x06;
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result += (destination & 0xf0) - (source & 0xf0);
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|
|
if(result > 0x99) result -= 0x60;
|
|
|
|
|
|
|
|
|
|
// Set all flags essentially as if this were normal subtraction.
|
|
|
|
|
zero_result_ |= result & 0xff;
|
|
|
|
|
extend_flag_ = carry_flag_ = result & ~0xff;
|
|
|
|
|
negative_flag_ = result & 0x80;
|
|
|
|
|
overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80;
|
|
|
|
|
|
|
|
|
|
// Store the result.
|
|
|
|
|
active_program_->destination->halves.low.halves.low = uint8_t(result);
|
|
|
|
|
} break;
|
|
|
|
|
|
2019-03-24 22:20:54 +00:00
|
|
|
/*
|
|
|
|
|
Development period debugging.
|
|
|
|
|
*/
|
2019-03-22 02:30:41 +00:00
|
|
|
default:
|
|
|
|
|
std::cerr << "Should do something with program operation " << int(active_program_->operation) << std::endl;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::SetMoveFlagsb):
|
2019-03-24 22:20:54 +00:00
|
|
|
zero_result_ = active_program_->source->halves.low.halves.low;
|
|
|
|
|
negative_flag_ = zero_result_ & 0x80;
|
2019-03-22 02:30:41 +00:00
|
|
|
overflow_flag_ = carry_flag_ = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::SetMoveFlagsw):
|
2019-03-24 22:20:54 +00:00
|
|
|
zero_result_ = active_program_->source->halves.low.full;
|
|
|
|
|
negative_flag_ = zero_result_ & 0x8000;
|
2019-03-22 02:30:41 +00:00
|
|
|
overflow_flag_ = carry_flag_ = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::SetMoveFlagsl):
|
2019-03-24 22:20:54 +00:00
|
|
|
zero_result_ = active_program_->source->full;
|
|
|
|
|
negative_flag_ = zero_result_ & 0x80000000;
|
2019-03-22 02:30:41 +00:00
|
|
|
overflow_flag_ = carry_flag_ = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Decrement1):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 1;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Decrement2):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 2;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Decrement4):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 4;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 4;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Increment1):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 1;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Increment2):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 2;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::Increment4):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 4;
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 4;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::SignExtendWord):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) {
|
|
|
|
|
active_program_->source->halves.high.full =
|
|
|
|
|
(active_program_->source->halves.low.full & 0x8000) ? 0xffff : 0x0000;
|
|
|
|
|
}
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) {
|
|
|
|
|
active_program_->destination->halves.high.full =
|
|
|
|
|
(active_program_->destination->halves.low.full & 0x8000) ? 0xffff : 0x0000;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::SignExtendByte):
|
|
|
|
|
if(active_micro_op_->action & MicroOp::SourceMask) {
|
|
|
|
|
active_program_->source->full = (active_program_->source->full & 0xff) |
|
|
|
|
|
(active_program_->source->full & 0x80) ? 0xffffff : 0x000000;
|
|
|
|
|
}
|
|
|
|
|
if(active_micro_op_->action & MicroOp::DestinationMask) {
|
|
|
|
|
active_program_->destination->full = (active_program_->destination->full & 0xff) |
|
|
|
|
|
(active_program_->destination->full & 0x80) ? 0xffffff : 0x000000;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2019-04-01 01:13:26 +00:00
|
|
|
case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask:
|
|
|
|
|
effective_address_[0] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CalcD16PC) | MicroOp::DestinationMask:
|
|
|
|
|
effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask | MicroOp::DestinationMask:
|
|
|
|
|
effective_address_[0] = int16_t(prefetch_queue_.halves.high.full) + program_counter_.full;
|
|
|
|
|
effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
|
|
|
|
|
break;
|
|
|
|
|
|
2019-03-22 02:30:41 +00:00
|
|
|
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
|
2019-03-23 01:43:51 +00:00
|
|
|
effective_address_[0] = int16_t(prefetch_queue_.halves.low.full) + active_program_->source->full;
|
2019-03-22 02:30:41 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
|
2019-03-23 01:43:51 +00:00
|
|
|
effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + active_program_->destination->full;
|
2019-03-22 02:30:41 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
|
|
|
|
|
effective_address_[0] = int16_t(prefetch_queue_.halves.high.full) + active_program_->source->full;
|
|
|
|
|
effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + active_program_->destination->full;
|
|
|
|
|
break;
|
|
|
|
|
|
2019-03-19 02:51:32 +00:00
|
|
|
#define CalculateD8AnXn(data, source, target) {\
|
|
|
|
|
const auto register_index = (data.full >> 12) & 7; \
|
|
|
|
|
const RegisterPair32 &displacement = (data.full & 0x8000) ? address_[register_index] : data_[register_index]; \
|
2019-03-27 02:07:28 +00:00
|
|
|
target.full = int8_t(data.halves.low) + source->full; \
|
2019-03-19 02:51:32 +00:00
|
|
|
\
|
|
|
|
|
if(data.full & 0x800) { \
|
2019-03-27 02:07:28 +00:00
|
|
|
target.full += displacement.halves.low.full; \
|
2019-03-19 02:51:32 +00:00
|
|
|
} else { \
|
2019-03-27 02:07:28 +00:00
|
|
|
target.full += displacement.full; \
|
2019-03-19 02:51:32 +00:00
|
|
|
} \
|
|
|
|
|
}
|
2019-03-22 02:30:41 +00:00
|
|
|
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
|
2019-03-23 01:43:51 +00:00
|
|
|
CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->source, effective_address_[0]);
|
2019-03-22 02:30:41 +00:00
|
|
|
} break;
|
2019-03-19 02:51:32 +00:00
|
|
|
|
2019-03-22 02:30:41 +00:00
|
|
|
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
|
2019-03-23 01:43:51 +00:00
|
|
|
CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->destination, effective_address_[1]);
|
2019-03-22 02:30:41 +00:00
|
|
|
} break;
|
2019-03-19 02:51:32 +00:00
|
|
|
|
2019-03-22 02:30:41 +00:00
|
|
|
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
|
|
|
|
|
CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]);
|
|
|
|
|
CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->destination, effective_address_[1]);
|
|
|
|
|
} break;
|
2019-03-19 02:51:32 +00:00
|
|
|
|
|
|
|
|
#undef CalculateD8AnXn
|
2019-03-19 15:53:37 +00:00
|
|
|
|
2019-03-25 03:05:57 +00:00
|
|
|
case int(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask:
|
2019-03-23 03:27:48 +00:00
|
|
|
// Assumption: this will be assembling right at the start of the instruction.
|
|
|
|
|
effective_address_[0] = prefetch_queue_.halves.low.full;
|
2019-03-22 02:30:41 +00:00
|
|
|
break;
|
2019-03-19 15:53:37 +00:00
|
|
|
|
2019-03-25 03:05:57 +00:00
|
|
|
case int(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask:
|
2019-03-23 03:27:48 +00:00
|
|
|
effective_address_[1] = prefetch_queue_.halves.low.full;
|
2019-03-23 01:43:51 +00:00
|
|
|
break;
|
|
|
|
|
|
2019-03-25 03:05:57 +00:00
|
|
|
case int(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask:
|
2019-03-23 01:43:51 +00:00
|
|
|
effective_address_[0] = prefetch_queue_.full;
|
|
|
|
|
break;
|
|
|
|
|
|
2019-03-25 03:05:57 +00:00
|
|
|
case int(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask:
|
2019-03-23 01:43:51 +00:00
|
|
|
effective_address_[1] = prefetch_queue_.full;
|
2019-03-22 02:30:41 +00:00
|
|
|
break;
|
2019-03-25 03:05:57 +00:00
|
|
|
|
|
|
|
|
case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask:
|
|
|
|
|
// Assumption: this will be assembling right at the start of the instruction.
|
2019-04-01 01:13:26 +00:00
|
|
|
source_bus_data_[0] = prefetch_queue_.halves.low.full;
|
2019-03-25 03:05:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask:
|
2019-04-01 01:13:26 +00:00
|
|
|
destination_bus_data_[0] = prefetch_queue_.halves.low.full;
|
2019-03-25 03:05:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask:
|
2019-04-01 01:13:26 +00:00
|
|
|
source_bus_data_[0] = prefetch_queue_.full;
|
2019-03-25 03:05:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask:
|
2019-04-01 01:13:26 +00:00
|
|
|
destination_bus_data_[0] = prefetch_queue_.full;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask:
|
|
|
|
|
effective_address_[0] = *active_program_->source;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::DestinationMask:
|
|
|
|
|
effective_address_[1] = *active_program_->destination;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask:
|
|
|
|
|
effective_address_[0] = *active_program_->source;
|
|
|
|
|
effective_address_[1] = *active_program_->destination;
|
2019-03-25 03:05:57 +00:00
|
|
|
break;
|
2019-03-22 02:30:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If we've got to a micro-op that includes bus steps, break out of this loop.
|
|
|
|
|
if(!active_micro_op_->is_terminal()) {
|
|
|
|
|
active_step_ = active_micro_op_->bus_program;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2019-03-13 02:46:31 +00:00
|
|
|
}
|
2019-03-22 02:30:41 +00:00
|
|
|
}
|
|
|
|
|
|
2019-03-13 02:46:31 +00:00
|
|
|
|
2019-03-22 02:30:41 +00:00
|
|
|
/*
|
|
|
|
|
PERFORM THE CURRENT BUS STEP'S MICROCYCLE.
|
|
|
|
|
*/
|
|
|
|
|
// Check for DTack if this isn't being treated implicitly.
|
|
|
|
|
if(!dtack_is_implicit) {
|
|
|
|
|
if(active_step_->microcycle.data_select_active() && !dtack_) {
|
|
|
|
|
// TODO: perform wait state.
|
|
|
|
|
continue;
|
2019-03-17 02:36:09 +00:00
|
|
|
}
|
2019-03-10 21:42:13 +00:00
|
|
|
}
|
2019-03-22 02:30:41 +00:00
|
|
|
|
|
|
|
|
// TODO: synchronous bus.
|
|
|
|
|
|
|
|
|
|
// TODO: check for bus error.
|
|
|
|
|
|
|
|
|
|
// Perform the microcycle.
|
|
|
|
|
remaining_duration -=
|
|
|
|
|
active_step_->microcycle.length +
|
|
|
|
|
bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
PERFORM THE BUS STEP'S ACTION.
|
|
|
|
|
*/
|
|
|
|
|
switch(active_step_->action) {
|
|
|
|
|
default:
|
|
|
|
|
std::cerr << "Unimplemented 68000 bus step action: " << int(active_step_->action) << std::endl;
|
|
|
|
|
return;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BusStep::Action::None: break;
|
|
|
|
|
|
2019-03-27 02:07:28 +00:00
|
|
|
case BusStep::Action::IncrementEffectiveAddress0: effective_address_[0].full += 2; break;
|
|
|
|
|
case BusStep::Action::IncrementEffectiveAddress1: effective_address_[1].full += 2; break;
|
|
|
|
|
case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break;
|
2019-03-22 02:30:41 +00:00
|
|
|
|
|
|
|
|
case BusStep::Action::AdvancePrefetch:
|
|
|
|
|
prefetch_queue_.halves.high = prefetch_queue_.halves.low;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Move to the next bus step.
|
|
|
|
|
++ active_step_;
|
2019-03-10 21:42:13 +00:00
|
|
|
}
|
2019-03-22 02:30:41 +00:00
|
|
|
|
|
|
|
|
half_cycles_left_to_run_ = remaining_duration;
|
2019-03-10 21:27:34 +00:00
|
|
|
}
|
2019-03-18 01:57:00 +00:00
|
|
|
|
|
|
|
|
template <class T, bool dtack_is_implicit> ProcessorState Processor<T, dtack_is_implicit>::get_state() {
|
|
|
|
|
write_back_stack_pointer();
|
|
|
|
|
|
|
|
|
|
State state;
|
|
|
|
|
memcpy(state.data, data_, sizeof(state.data));
|
|
|
|
|
memcpy(state.address, address_, sizeof(state.address));
|
|
|
|
|
state.user_stack_pointer = stack_pointers_[0].full;
|
|
|
|
|
state.supervisor_stack_pointer = stack_pointers_[1].full;
|
|
|
|
|
|
2019-03-24 22:20:54 +00:00
|
|
|
state.status = get_status();
|
2019-03-18 01:57:00 +00:00
|
|
|
|
|
|
|
|
return state;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::set_state(const ProcessorState &state) {
|
|
|
|
|
memcpy(data_, state.data, sizeof(state.data));
|
|
|
|
|
memcpy(address_, state.address, sizeof(state.address));
|
|
|
|
|
stack_pointers_[0].full = state.user_stack_pointer;
|
|
|
|
|
stack_pointers_[1].full = state.supervisor_stack_pointer;
|
|
|
|
|
|
2019-03-24 22:20:54 +00:00
|
|
|
set_status(state.status);
|
2019-03-22 23:34:17 +00:00
|
|
|
|
|
|
|
|
address_[7] = stack_pointers_[is_supervisor_];
|
2019-03-18 01:57:00 +00:00
|
|
|
}
|
2019-03-24 22:20:54 +00:00
|
|
|
|
|
|
|
|
#undef get_status
|
|
|
|
|
#undef set_status
|
