2017-05-17 01:19:17 +00:00
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//
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// Z80AllRAM.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#ifndef Z80AllRAM_hpp
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#define Z80AllRAM_hpp
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#include "Z80.hpp"
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2017-05-17 01:28:17 +00:00
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#include "../AllRAMProcessor.hpp"
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2017-05-17 01:19:17 +00:00
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namespace CPU {
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namespace Z80 {
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2017-05-17 01:28:17 +00:00
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class AllRAMProcessor:
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2017-05-31 02:41:23 +00:00
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public ::CPU::AllRAMProcessor {
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2017-05-17 01:28:17 +00:00
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2017-05-17 01:19:17 +00:00
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public:
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2017-05-31 02:41:23 +00:00
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static AllRAMProcessor *Processor();
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2017-05-22 23:24:11 +00:00
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struct MemoryAccessDelegate {
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2017-07-28 00:17:13 +00:00
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virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) = 0;
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2017-05-22 23:24:11 +00:00
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};
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2017-05-31 02:41:23 +00:00
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inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
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2017-05-22 23:24:11 +00:00
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delegate_ = delegate;
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}
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2017-07-28 02:05:29 +00:00
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virtual void run_for(const Cycles cycles) = 0;
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2017-05-31 02:41:23 +00:00
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virtual uint16_t get_value_of_register(Register r) = 0;
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virtual void set_value_of_register(Register r, uint16_t value) = 0;
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virtual bool get_halt_line() = 0;
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2017-06-02 02:33:05 +00:00
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virtual void reset_power_on() = 0;
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2017-06-23 01:09:26 +00:00
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2017-06-03 21:41:45 +00:00
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virtual void set_interrupt_line(bool value) = 0;
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virtual void set_non_maskable_interrupt_line(bool value) = 0;
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2017-06-23 01:09:26 +00:00
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virtual void set_wait_line(bool value) = 0;
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2017-05-31 02:41:23 +00:00
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protected:
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2017-05-22 23:24:11 +00:00
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MemoryAccessDelegate *delegate_;
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2017-05-31 02:41:23 +00:00
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AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
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2017-05-17 01:19:17 +00:00
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};
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}
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}
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#endif /* Z80AllRAM_hpp */
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