2017-05-17 01:19:17 +00:00
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//
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// Z80AllRAM.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "Z80AllRAM.hpp"
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#include <algorithm>
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using namespace CPU::Z80;
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2017-05-31 02:41:23 +00:00
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namespace {
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2017-05-17 01:19:17 +00:00
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2017-08-03 02:09:59 +00:00
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class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
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2017-05-31 02:41:23 +00:00
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public:
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2017-08-03 02:09:59 +00:00
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ConcreteAllRAMProcessor() : AllRAMProcessor(), z80_(*this) {}
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2017-05-31 02:41:23 +00:00
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2017-07-28 01:38:50 +00:00
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inline HalfCycles perform_machine_cycle(const PartialMachineCycle &cycle) {
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2017-07-28 00:17:13 +00:00
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timestamp_ += cycle.length;
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2017-06-22 00:32:08 +00:00
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if(!cycle.is_terminal()) {
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2017-07-28 01:38:50 +00:00
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return HalfCycles(0);
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2017-06-22 00:32:08 +00:00
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}
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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2017-07-28 00:17:13 +00:00
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case PartialMachineCycle::ReadOpcode:
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2017-06-22 00:32:08 +00:00
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check_address_for_trap(address);
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Read:
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2017-06-22 00:32:08 +00:00
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*cycle.value = memory_[address];
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break;
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Write:
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2017-06-22 00:32:08 +00:00
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memory_[address] = *cycle.value;
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break;
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Output:
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2017-06-22 00:32:08 +00:00
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break;
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Input:
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2017-06-22 00:32:08 +00:00
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// This logic is selected specifically because it seems to match
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// the FUSE unit tests. It might need factoring out.
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*cycle.value = address >> 8;
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break;
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Internal:
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case PartialMachineCycle::Refresh:
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2017-06-22 00:32:08 +00:00
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break;
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2017-06-22 00:38:08 +00:00
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case PartialMachineCycle::Interrupt:
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2017-06-22 00:32:08 +00:00
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// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
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// arbitrary.
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*cycle.value = 0x21;
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break;
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default:
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printf("???\n");
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break;
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}
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2017-05-31 02:41:23 +00:00
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if(delegate_ != nullptr) {
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2017-07-28 00:17:13 +00:00
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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2017-05-31 02:41:23 +00:00
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}
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2017-07-28 01:38:50 +00:00
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return HalfCycles(0);
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2017-05-31 02:41:23 +00:00
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}
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2017-07-28 02:05:29 +00:00
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void run_for(const Cycles cycles) {
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2017-08-03 02:09:59 +00:00
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z80_.run_for(cycles);
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2017-05-31 02:41:23 +00:00
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}
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uint16_t get_value_of_register(Register r) {
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2017-08-03 02:09:59 +00:00
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return z80_.get_value_of_register(r);
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2017-05-31 02:41:23 +00:00
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}
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void set_value_of_register(Register r, uint16_t value) {
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2017-08-03 02:09:59 +00:00
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z80_.set_value_of_register(r, value);
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2017-05-31 02:41:23 +00:00
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}
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bool get_halt_line() {
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2017-08-03 02:09:59 +00:00
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return z80_.get_halt_line();
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2017-05-31 02:41:23 +00:00
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}
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2017-06-02 02:33:05 +00:00
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void reset_power_on() {
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2017-08-03 02:09:59 +00:00
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return z80_.reset_power_on();
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2017-06-02 02:33:05 +00:00
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}
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2017-06-03 21:41:45 +00:00
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void set_interrupt_line(bool value) {
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2017-08-03 02:09:59 +00:00
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z80_.set_interrupt_line(value);
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2017-06-03 21:41:45 +00:00
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}
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void set_non_maskable_interrupt_line(bool value) {
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2017-08-03 02:09:59 +00:00
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z80_.set_non_maskable_interrupt_line(value);
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2017-06-03 21:41:45 +00:00
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}
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2017-06-23 01:09:26 +00:00
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void set_wait_line(bool value) {
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2017-08-03 02:09:59 +00:00
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z80_.set_wait_line(value);
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2017-06-23 01:09:26 +00:00
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}
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2017-08-03 02:09:59 +00:00
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private:
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2017-08-22 01:56:42 +00:00
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CPU::Z80::Processor<ConcreteAllRAMProcessor, false> z80_;
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2017-05-31 02:41:23 +00:00
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};
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}
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AllRAMProcessor *AllRAMProcessor::Processor() {
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return new ConcreteAllRAMProcessor;
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2017-05-17 01:19:17 +00:00
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}
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