2017-05-17 01:28:17 +00:00
|
|
|
//
|
|
|
|
// AllRAMProcessor.cpp
|
|
|
|
// Clock Signal
|
|
|
|
//
|
|
|
|
// Created by Thomas Harte on 16/05/2017.
|
2018-05-13 19:19:52 +00:00
|
|
|
// Copyright 2017 Thomas Harte. All rights reserved.
|
2017-05-17 01:28:17 +00:00
|
|
|
//
|
|
|
|
|
|
|
|
#include "AllRAMProcessor.hpp"
|
|
|
|
|
|
|
|
using namespace CPU;
|
|
|
|
|
2017-11-11 20:28:40 +00:00
|
|
|
AllRAMProcessor::AllRAMProcessor(std::size_t memory_size) :
|
2017-05-17 01:28:17 +00:00
|
|
|
memory_(memory_size),
|
2017-06-04 01:54:42 +00:00
|
|
|
traps_(memory_size, false),
|
2017-05-17 01:28:17 +00:00
|
|
|
timestamp_(0) {}
|
|
|
|
|
2020-10-12 01:18:01 +00:00
|
|
|
void AllRAMProcessor::set_data_at_address(size_t start_address, std::size_t length, const uint8_t *data) {
|
|
|
|
const size_t end_address = std::min(start_address + length, memory_.size());
|
|
|
|
memcpy(&memory_[start_address], data, end_address - start_address);
|
2017-05-17 01:28:17 +00:00
|
|
|
}
|
|
|
|
|
2020-10-12 01:18:01 +00:00
|
|
|
void AllRAMProcessor::get_data_at_address(size_t start_address, std::size_t length, uint8_t *data) {
|
|
|
|
const size_t end_address = std::min(start_address + length, memory_.size());
|
|
|
|
memcpy(data, &memory_[start_address], end_address - start_address);
|
2017-05-20 01:53:39 +00:00
|
|
|
}
|
|
|
|
|
2017-07-28 00:17:13 +00:00
|
|
|
HalfCycles AllRAMProcessor::get_timestamp() {
|
2017-05-17 01:28:17 +00:00
|
|
|
return timestamp_;
|
|
|
|
}
|
2017-05-20 01:20:28 +00:00
|
|
|
|
|
|
|
void AllRAMProcessor::set_trap_handler(TrapHandler *trap_handler) {
|
|
|
|
trap_handler_ = trap_handler;
|
|
|
|
}
|
|
|
|
|
|
|
|
void AllRAMProcessor::add_trap_address(uint16_t address) {
|
2017-06-04 01:54:42 +00:00
|
|
|
traps_[address] = true;
|
2017-05-20 01:20:28 +00:00
|
|
|
}
|