2022-05-16 15:44:16 +00:00
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//
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// 68000Mk2Storage.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2Storage_h
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#define _8000Mk2Storage_h
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2022-05-16 20:57:40 +00:00
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#include "../../../InstructionSets/M68k/Decoder.hpp"
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#include "../../../InstructionSets/M68k/Perform.hpp"
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#include "../../../InstructionSets/M68k/Status.hpp"
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namespace CPU {
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namespace MC68000Mk2 {
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struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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/// States for the state machine which are named by
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/// me for their purpose rather than automatically by file position.
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/// These are negative to avoid ambiguity with the other group.
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enum State: int {
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Reset = -1,
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Decode = -2,
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WaitForDTACK = -3,
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FetchOperand = -4,
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StoreOperand = -5,
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// Various different effective address calculations.
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CalculateAnDn = -5,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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Perform_np = -6,
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Perform_np_n = -7,
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};
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int state_ = State::Reset;
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/// Counts time left on the clock before the current batch of processing
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/// is complete; may be less than zero.
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HalfCycles time_remaining_;
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/// Current supervisor state, for direct provision to the bus handler.
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int is_supervisor_ = 1;
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// A decoder for instructions, plus all collected information about the
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// current instruction.
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
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InstructionSet::M68k::Preinstruction instruction_;
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uint16_t opcode_;
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uint8_t operand_flags_;
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uint32_t instruction_address_;
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// Register state.
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InstructionSet::M68k::Status status_;
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SlicedInt32 program_counter_;
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SlicedInt32 registers_[16]; // D0–D7 followed by A0–A7.
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SlicedInt32 stack_pointers_[2];
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/// Current state of the DTACK input.
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bool dtack_ = false;
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/// Current state of the VPA input.
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bool vpa_ = false;
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/// Current state of the BERR input.
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bool berr_ = false;
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/// Contains the prefetch queue; the most-recently fetched thing is the
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/// low portion of this word, and the thing fetched before that has
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/// proceeded to the high portion.
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SlicedInt32 prefetch_;
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// Temporary storage for the current instruction's operands
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// and the corresponding effective addresses.
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CPU::SlicedInt32 operand_[2];
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uint32_t effective_address_[2];
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/// If currently in the wait-for-DTACK state, this indicates where to go
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/// upon receipt of DTACK or VPA. BERR will automatically segue
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/// into the proper exception.
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int post_dtack_state_ = 0;
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/// The perform state for this operation.
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int perform_state_ = 0;
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/// When fetching or storing operands, this is the next one to fetch
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/// or store.
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int next_operand_ = 0;
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/// Storage for a temporary address, which can't be a local because it'll
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/// be used to populate microcycles, which may persist beyond an entry
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/// and exit of run_for (especially between an address announcement, and
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/// a data select).
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uint32_t temporary_address_ = 0;
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// Flow controller... all TODO.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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template <typename IntT> void did_mulu(IntT) {}
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template <typename IntT> void did_muls(IntT) {}
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void did_chk(bool, bool) {}
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void did_shift(int) {}
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template <bool did_overflow> void did_divu(uint32_t, uint32_t) {}
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template <bool did_overflow> void did_divs(int32_t, int32_t) {}
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void did_bit_op(int) {}
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inline void did_update_status();
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template <typename IntT> void complete_bcc(bool, IntT) {}
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void complete_dbcc(bool, bool, int16_t) {}
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void bsr(uint32_t) {}
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void jsr(uint32_t) {}
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void jmp(uint32_t) {}
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void rtr() {}
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void rte() {}
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void rts() {}
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void stop() {}
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void reset() {}
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void link(Preinstruction, uint32_t) {}
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void unlink(uint32_t &) {}
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void pea(uint32_t) {}
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void move_to_usp(uint32_t) {}
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void move_from_usp(uint32_t &) {}
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void tas(Preinstruction, uint32_t) {}
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template <typename IntT> void movep(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toM(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toR(Preinstruction, uint32_t, uint32_t) {}
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template <bool use_current_instruction_pc = true> void raise_exception(int) {}
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// Some microcycles that will be modified as required and used in the main loop;
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// the semantics of a switch statement make in-place declarations awkward and
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// some of these may persist across multiple calls to run_for.
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Microcycle idle{0};
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// Read a data word.
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Microcycle read_word_data_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData
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};
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Microcycle read_word_data {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
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};
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// Read a program word. All accesses via the program counter are word sized.
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Microcycle read_program_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsProgram
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};
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Microcycle read_program {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsProgram
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};
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// Holding spot when awaiting DTACK/etc.
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Microcycle awaiting_dtack;
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};
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}
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}
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#endif /* _8000Mk2Storage_h */
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