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88 lines
1.9 KiB
Plaintext
88 lines
1.9 KiB
Plaintext
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//
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// 68000Tests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 13/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include <array>
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#include <cassert>
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#include "68000.hpp"
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/*!
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Provides a 68000 with 64kb of RAM in its low address space;
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/RESET will put the supervisor stack pointer at 0xFFFF and
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begin execution at 0x0400.
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*/
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class RAM68000: public CPU::MC68000::BusHandler {
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public:
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RAM68000() : m68000_(*this) {
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ram_.resize(32768);
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// Setup the /RESET vector.
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ram_[0] = 0;
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ram_[1] = 0xffff;
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ram_[2] = 0;
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ram_[3] = 0x0400;
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}
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void set_program(const std::vector<uint16_t> &program) {
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memcpy(&ram_[512], program.data(), program.size() * sizeof(uint16_t));
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}
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void run_for(HalfCycles cycles) {
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m68000_.run_for(cycles);
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}
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
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uint32_t address = cycle.address ? (*cycle.address) & 0x00fffffe : 0;
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switch(cycle.operation & (CPU::MC68000::Microcycle::LowerData | CPU::MC68000::Microcycle::UpperData)) {
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case 0: break;
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case CPU::MC68000::Microcycle::LowerData:
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cycle.value->halves.low = ram_[address >> 1] >> 8;
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break;
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case CPU::MC68000::Microcycle::UpperData:
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cycle.value->halves.high = ram_[address >> 1] & 0xff;
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break;
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case CPU::MC68000::Microcycle::UpperData | CPU::MC68000::Microcycle::LowerData:
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cycle.value->full = ram_[address >> 1];
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break;
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}
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return HalfCycles(0);
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}
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private:
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CPU::MC68000::Processor<RAM68000, true> m68000_;
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std::vector<uint16_t> ram_;
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};
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@interface M68000Tests : XCTestCase
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@end
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@implementation M68000Tests {
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std::unique_ptr<RAM68000> _machine;
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}
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- (void)setUp {
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_machine.reset(new RAM68000());
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}
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- (void)tearDown {
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_machine.reset();
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}
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- (void)testABCD {
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_machine->set_program({
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0xc100 // ABCD D0, D0
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});
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_machine->run_for(HalfCycles(400));
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}
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@end
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