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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-25 18:30:21 +00:00

This is probably a valid test. But I'm not completely sure. Time to figure out what's happening on the 1540 end.

This commit is contained in:
Thomas Harte 2016-07-09 18:01:04 -04:00
parent cd84c35552
commit 01746f0512

View File

@ -32,16 +32,20 @@ class C1540Tests: XCTestCase {
c1540.runForCycles(256) // this isn't time limited on real hardware c1540.runForCycles(256) // this isn't time limited on real hardware
XCTAssert(c1540.dataLine == true, "Listener should have let data line go high again") XCTAssert(c1540.dataLine == true, "Listener should have let data line go high again")
for _ in 0..<8 { // set up for byte transfer
// ensure the closk is true again c1540.clockLine = false
c1540.clockLine = true c1540.dataLine = true
c1540.runForCycles(40) c1540.runForCycles(40)
// transmit bits
for _ in 0..<8 {
// load data line // load data line
c1540.dataLine = (shiftedValue & 1) == 0 c1540.dataLine = (shiftedValue & 1) == 0
shiftedValue >>= 1 shiftedValue >>= 1
// toggle clock // toggle clock
c1540.clockLine = true
c1540.runForCycles(40)
c1540.clockLine = false c1540.clockLine = false
c1540.runForCycles(40) c1540.runForCycles(40)
} }