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It sounds like the two sync signals are exclusive ORd.
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@ -199,31 +199,30 @@ void Machine::output_pixels(unsigned int count)
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}
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}
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// logic: if in vsync, output that; otherwise if in vblank then output that;
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// otherwise output a pixel
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if(_vSyncEnabled) {
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state = (_horizontalTimer < start_of_sync) ? OutputState::Sync : OutputState::Blank;
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} else {
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// blank is decoded as 68 counts; sync and colour burst as 16 counts
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// blank is decoded as 68 counts; sync and colour burst as 16 counts
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// 4 blank
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// 4 sync
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// 9 'blank'; colour burst after 4
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// 40 pixels
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// 4 blank
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// 4 sync
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// 9 'blank'; colour burst after 4
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// 40 pixels
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// it'll be about 43 cycles from start of hsync to start of visible frame, so...
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// guesses, until I can find information: 26 cycles blank, 16 sync, 40 blank, 160 pixels
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if (_horizontalTimer < (_vBlankExtend ? 152 : 160)) {
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if(_vBlankEnabled) {
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state = OutputState::Blank;
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} else {
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state = OutputState::Pixel;
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}
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// it'll be about 43 cycles from start of hsync to start of visible frame, so...
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// guesses, until I can find information: 26 cycles blank, 16 sync, 40 blank, 160 pixels
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if (_horizontalTimer < (_vBlankExtend ? 152 : 160)) {
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if(_vBlankEnabled) {
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state = OutputState::Blank;
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} else {
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state = OutputState::Pixel;
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}
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else if (_horizontalTimer < end_of_sync) state = OutputState::Blank;
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else if (_horizontalTimer < start_of_sync) state = OutputState::Sync;
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else state = OutputState::Blank;
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}
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else if (_horizontalTimer < end_of_sync) state = OutputState::Blank;
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else if (_horizontalTimer < start_of_sync) state = OutputState::Sync;
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else state = OutputState::Blank;
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// logic: if vsync is enabled, output the opposite of the automatic hsync output
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if(_vSyncEnabled) {
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state = (state = OutputState::Sync) ? OutputState::Blank : OutputState::Sync;
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}
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_lastOutputStateDuration++;
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