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Corrects RTS behaviour: the return address on the stack is off by one.

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Dormann's tests now proceed to a BRK.
This commit is contained in:
Thomas Harte 2020-10-08 16:55:45 -04:00
parent 907c3374c3
commit 054e0af071
3 changed files with 9 additions and 3 deletions
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5
Processors/65816/Implementation/65816Implementation.hpp
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@ -455,6 +455,10 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
pc_ = data_buffer_.value; pc_ = data_buffer_.value;
break; break;
case RTS:
pc_ = data_buffer_.value + 1;
break;
case JSL: case JSL:
program_bank_ = instruction_buffer_.value & 0xff0000; program_bank_ = instruction_buffer_.value & 0xff0000;
[[fallthrough]]; [[fallthrough]];
@ -678,7 +682,6 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
} break; } break;
// TODO: // TODO:
// PHK,
// TRB, TSB, // TRB, TSB,
// REP, SEP, // REP, SEP,
// XCE, XBA, // XCE, XBA,

4
Processors/65816/Implementation/65816Storage.cpp
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@ -661,7 +661,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CyclePull); // PCH target(CyclePull); // PCH
target(CycleAccessStack); // IO target(CycleAccessStack); // IO
target(OperationPerform); // [JMP, to perform the RTS] target(OperationPerform); // [RTS]
} }
// 22i. Stack; s, RTL. // 22i. Stack; s, RTL.
@ -812,7 +812,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x5e LSR a, x */ op(absolute_x_rmw, LSR); /* 0x5e LSR a, x */ op(absolute_x_rmw, LSR);
/* 0x5f EOR al, x */ op(absolute_long_x, EOR); /* 0x5f EOR al, x */ op(absolute_long_x, EOR);
/* 0x60 RTS s */ op(stack_rts, JMPind); // [sic]; loads the PC from data as per an RTS. /* 0x60 RTS s */ op(stack_rts, RTS);
/* 0x61 ADC (d, x) */ op(direct_indexed_indirect, ADC); /* 0x61 ADC (d, x) */ op(direct_indexed_indirect, ADC);
/* 0x62 PER s */ op(stack_per, NOP); /* 0x62 PER s */ op(stack_per, NOP);
/* 0x63 ADC d, s */ op(stack_relative, ADC); /* 0x63 ADC d, s */ op(stack_relative, ADC);

3
Processors/65816/Implementation/65816Storage.hpp
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@ -191,6 +191,9 @@ enum Operation: uint8_t {
/// placing the old PC into the data buffer (and only the PC; PBR not included). /// placing the old PC into the data buffer (and only the PC; PBR not included).
JSL, JSL,
/// Loads the PC with the contents of the data buffer + 1.
RTS,
/// i.e. jump to vector. TODO: is this really distinct from JMP? I'm assuming so for now, /// i.e. jump to vector. TODO: is this really distinct from JMP? I'm assuming so for now,
/// as I assume the PBR is implicitly modified. But then is it just JML? We'll see. /// as I assume the PBR is implicitly modified. But then is it just JML? We'll see.
BRK, BRK,