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https://github.com/TomHarte/CLK.git
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The 5/3 split of microcycles appears not accurately to model when lines are tested.
Therefore I've reverted to a more normative 4:4 form.
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@ -208,13 +208,11 @@ struct ProcessorStorageConstructor {
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// Fetch SSP.
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// Fetch SSP.
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if(token == "nF" || token == "nf") {
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if(token == "nF" || token == "nf") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
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step.microcycle.value = isupper(token[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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steps.push_back(step);
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@ -224,13 +222,11 @@ struct ProcessorStorageConstructor {
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// Fetch exception vector.
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// Fetch exception vector.
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if(token == "nV" || token == "nv") {
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if(token == "nV" || token == "nv") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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step.microcycle.value = isupper(token[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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steps.push_back(step);
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@ -240,14 +236,12 @@ struct ProcessorStorageConstructor {
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// Fetch from the program counter into the prefetch queue.
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// Fetch from the program counter into the prefetch queue.
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if(token == "np") {
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if(token == "np") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.action = Action::AdvancePrefetch;
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementProgramCounter;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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steps.push_back(step);
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@ -272,13 +266,11 @@ struct ProcessorStorageConstructor {
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assert(address_iterator != addresses.end());
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assert(address_iterator != addresses.end());
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | (is_read ? Microcycle::Read : 0) | (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte);
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step.microcycle.operation = Microcycle::SameAddress | (is_read ? Microcycle::Read : 0) | (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte);
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if(post_adjustment) {
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if(post_adjustment) {
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// nr and nR should affect address 0; nw, nW, nrd and nRd should affect address 1.
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// nr and nR should affect address 0; nw, nW, nrd and nRd should affect address 1.
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@ -317,13 +309,11 @@ struct ProcessorStorageConstructor {
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// A stack write.
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// A stack write.
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if(token == "nS" || token == "ns") {
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if(token == "nS" || token == "ns") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress;
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step.microcycle.operation = Microcycle::NewAddress;
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step.microcycle.address = &storage_.effective_address_[1].full;
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step.microcycle.address = &storage_.effective_address_[1].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.destination_bus_data_[0].halves.high : &storage_.destination_bus_data_[0].halves.low;
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step.microcycle.value = isupper(token[1]) ? &storage_.destination_bus_data_[0].halves.high : &storage_.destination_bus_data_[0].halves.low;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectWord;
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step.action = Action::DecrementEffectiveAddress1;
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step.action = Action::DecrementEffectiveAddress1;
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steps.push_back(step);
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steps.push_back(step);
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@ -335,13 +325,11 @@ struct ProcessorStorageConstructor {
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if(token == "nU" || token == "nu") {
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if(token == "nU" || token == "nu") {
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RegisterPair32 *const scratch_data = &storage_.source_bus_data_[0];
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RegisterPair32 *const scratch_data = &storage_.source_bus_data_[0];
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read;
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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steps.push_back(step);
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