mirror of
https://github.com/TomHarte/CLK.git
synced 2024-12-25 18:30:21 +00:00
Ensures the Mac uses auto vectored interrupts.
This commit is contained in:
parent
3bb8d6717f
commit
0848fc7e03
@ -176,10 +176,19 @@ class ConcreteMachine:
|
||||
if(!(operation & Microcycle::Read) || word_address >= 0x300000) operation = 0;
|
||||
}
|
||||
|
||||
switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
|
||||
const auto masked_operation = operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge);
|
||||
switch(masked_operation) {
|
||||
default:
|
||||
break;
|
||||
|
||||
// Catches the deliberation set of operation to 0 above.
|
||||
case 0: break;
|
||||
|
||||
case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
|
||||
// The Macintosh uses autovectored interrupts.
|
||||
mc68000_.set_is_peripheral_address(true);
|
||||
break;
|
||||
|
||||
case Microcycle::SelectWord | Microcycle::Read:
|
||||
cycle.value->full = memory_base[word_address];
|
||||
break;
|
||||
|
@ -272,7 +272,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
|
||||
}
|
||||
|
||||
#ifdef LOG_TRACE
|
||||
// should_log |= ((program_counter_.full - 4) == 0x4058d8);
|
||||
should_log |= ((program_counter_.full - 4) == 0x4058d8);
|
||||
#endif
|
||||
|
||||
if(instructions[decoded_instruction_.full].micro_operations) {
|
||||
@ -1859,6 +1859,9 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
|
||||
break;
|
||||
|
||||
case int(MicroOp::Action::PrepareINTVector):
|
||||
// Let bus error go back to causing exceptions.
|
||||
is_starting_interrupt_ = false;
|
||||
|
||||
// Bus error => spurious interrupt.
|
||||
if(bus_error_) {
|
||||
effective_address_[0].full = 24 << 2;
|
||||
@ -1873,9 +1876,6 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
|
||||
|
||||
// Otherwise, the vector is whatever we were just told it is.
|
||||
effective_address_[0].full = source_bus_data_[0].halves.low.halves.low << 2;
|
||||
|
||||
// Let bus error go back to causing exceptions.
|
||||
is_starting_interrupt_ = false;
|
||||
break;
|
||||
|
||||
case int(MicroOp::Action::CopyNextWord):
|
||||
|
Loading…
Reference in New Issue
Block a user