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https://github.com/TomHarte/CLK.git
synced 2024-09-26 11:55:15 +00:00
Switch to macro blocks of execution; flail around audio.
This commit is contained in:
Thomas Harte
parent
3a2d9c6082
commit
08673ff021
@ -194,9 +194,56 @@ private:
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static constexpr uint8_t MACK = 0b0011'0010; // Last data byte acknowledge.
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static constexpr uint8_t SMAK = 0b0011'0011; // Last data byte acknowledge.
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static constexpr uint8_t PRST = 0b0010'0001; // Does nothing.
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};
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struct Audio {
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void set_next_end(uint32_t value) {
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next_.end = value;
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}
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void set_next_start(uint32_t value) {
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next_.start = value;
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next_buffer_valid_ = true;
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}
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bool interrupt() const {
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return !next_buffer_valid_;
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}
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void swap() {
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current_.start = next_.start;
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std::swap(current_.end, next_.end);
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next_buffer_valid_ = false;
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halted_ = false;
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}
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bool tick() {
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if(halted_) {
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return false;
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}
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current_.start += 16;
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if(current_.start == current_.end) {
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if(next_buffer_valid_) {
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swap();
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return true;
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} else {
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halted_ = true;
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return false;
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}
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}
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return false;
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}
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private:
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bool next_buffer_valid_ = false;
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bool halted_ = true; // This is a bit of a guess.
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struct Buffer {
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uint32_t start = 0, end = 0;
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};
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Buffer current_, next_;
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};
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struct Video {
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void write(uint32_t value) {
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const auto target = (value >> 24) & 0xfc;
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@ -327,7 +374,7 @@ namespace InterruptRequests {
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static constexpr int FIQ = 0x02;
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};
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struct Interrupts {
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struct InputOutput {
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int interrupt_mask() const {
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return
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((irq_a_.request() | irq_b_.request()) ? InterruptRequests::IRQ : 0) |
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@ -577,7 +624,7 @@ struct Interrupts {
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return true;
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}
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Interrupts() : keyboard_(serial_) {
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InputOutput() : keyboard_(serial_) {
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irq_a_.status = IRQA::SetAlways | IRQA::PowerOnReset;
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irq_b_.status = 0x00;
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fiq_.status = 0x80; // 'set always'.
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@ -585,6 +632,27 @@ struct Interrupts {
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i2c_.add_peripheral(&cmos_, 0xa0);
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}
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Audio &audio() {
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return audio_;
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}
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bool tick_audio() {
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if(audio_.tick()) {
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if(audio_.interrupt()) {
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irq_b_.apply(IRQB::SoundBufferPointerUsed);
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} else {
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irq_b_.clear(IRQB::SoundBufferPointerUsed);
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}
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return true;
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}
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return false;
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}
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void swap_audio() {
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audio_.swap();
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irq_b_.clear(IRQB::SoundBufferPointerUsed);
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}
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private:
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// IRQA, IRQB and FIQ states.
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struct Interrupt {
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@ -620,6 +688,9 @@ private:
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// The I2C bus.
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I2C::Bus i2c_;
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CMOSRAM cmos_;
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// Audio.
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Audio audio_;
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};
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/// Primarily models the MEMC.
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@ -654,11 +725,47 @@ struct Memory {
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}
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switch(write_zones_[(address >> 21) & 31]) {
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case Zone::DMAAndMEMC:
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if((address & 0b1110'0000'0000'0000'0000) == 0b1110'0000'0000'0000'0000) {
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// "The parameters are encoded into the processor address lines".
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case Zone::DMAAndMEMC: {
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const auto buffer_address = [](uint32_t source) -> uint32_t {
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return (source & 0x1fffc0) << 2;
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};
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// The MEMC itself isn't on the data bus; all values below should be taken from `address`.
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switch((address >> 17) & 0b111) {
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case 0b000:
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logger.error().append("TODO: DMA/MEMC Vinit = %04x", address & 0x1fffc0);
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return true;
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case 0b001:
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logger.error().append("TODO: DMA/MEMC Vstart = %04x", address & 0x1fffc0);
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return true;
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case 0b010:
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logger.error().append("TODO: DMA/MEMC Vend = %04x", address & 0x1fffc0);
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return true;
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case 0b011:
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logger.error().append("TODO: DMA/MEMC Cinit = %04x", address & 0x1fffc0);
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return true;
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case 0b100:
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logger.error().append("TODO: DMA/MEMC Sstart = %04x", address & 0x1fffc0);
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ioc_.audio().set_next_start(buffer_address(address));
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return true;
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case 0b101:
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logger.error().append("TODO: DMA/MEMC SendN = %04x", address & 0x1fffc0);
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ioc_.audio().set_next_end(buffer_address(address));
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return true;
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case 0b110:
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logger.error().append("TODO: DMA/MEMC Sptr");
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ioc_.swap_audio();
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return true;
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case 0b111:
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os_mode_ = address & (1 << 12);
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sound_dma_enable_ = address & (1 << 11);
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audio_dma_enable_ = address & (1 << 11);
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video_dma_enable_ = address & (1 << 10);
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switch((address >> 8) & 3) {
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default:
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@ -673,14 +780,11 @@ struct Memory {
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low_rom_access_time_ = ROMAccessTime((address >> 4) & 3);
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page_size_ = PageSize((address >> 2) & 3);
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logger.info().append("MEMC Control: %08x -> OS:%d sound:%d video:%d refresh:%d high:%d low:%d size:%d", address, os_mode_, sound_dma_enable_, video_dma_enable_, dynamic_ram_refresh_, high_rom_access_time_, low_rom_access_time_, page_size_);
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logger.info().append("MEMC Control: %08x -> OS:%d audio:%d video:%d refresh:%d high:%d low:%d size:%d", address, os_mode_, audio_dma_enable_, video_dma_enable_, dynamic_ram_refresh_, high_rom_access_time_, low_rom_access_time_, page_size_);
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map_dirty_ = true;
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return true;
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} else {
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logger.error().append("TODO: DMA/MEMC %08x to %08x", source, address);
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}
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break;
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} break;
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case Zone::LogicallyMappedRAM: {
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const auto item = logical_ram<IntT, false>(address, mode);
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@ -784,11 +888,17 @@ struct Memory {
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return ioc_.tick_timers();
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}
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bool tick_audio() {
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// TODO: does disabling audio DMA pause output, or leave it ticking and merely
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// stop allowing it to use the bus?
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return ioc_.tick_audio();
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}
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private:
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bool has_moved_rom_ = false;
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std::array<uint8_t, 4*1024*1024> ram_{};
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std::array<uint8_t, 2*1024*1024> rom_;
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Interrupts ioc_;
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InputOutput ioc_;
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Video vidc_;
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IOCWriteDelegateT &ioc_write_delegate_;
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@ -810,7 +920,7 @@ struct Memory {
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// Control register values.
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bool os_mode_ = false;
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bool sound_dma_enable_ = false;
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bool audio_dma_enable_ = false;
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bool video_dma_enable_ = false; // "Unaffected" by reset, so here picked arbitrarily.
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enum class DynamicRAMRefresh {
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@ -1009,12 +1119,60 @@ class ConcreteMachine:
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public MachineTypes::TimedMachine,
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public MachineTypes::ScanProducer
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{
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private:
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// TODO: pick a sensible clock rate; this is just code for '24 MIPS, please'.
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static constexpr int ClockRate = 24'000'000;
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// Timers tick at 2Mhz, so figure out the proper divider for that.
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static constexpr int TimerTarget = ClockRate / 2'000'000;
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int timer_divider_ = TimerTarget;
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// Runs for 24 cycles, distributing calls to the various ticking subsystems
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// 'correctly' (i.e. correctly for the approximation in use).
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//
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// The implementation of this is coupled to the ClockRate above, hence its
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// appearance here.
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void macro_tick() {
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macro_counter_ -= 24;
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// This is a 24-cycle window, so at 24Mhz macro_tick() is called at 1Mhz.
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// Hence, required ticks are:
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//
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// * CPU: 24;
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// * video: 12; [TODO]
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// * timers: 2;
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// * audio: 1. [TODO]
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_timers();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_cpu();
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tick_timers();
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tick_audio();
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}
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int macro_counter_ = 0;
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public:
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ConcreteMachine(
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@ -1053,17 +1211,17 @@ class ConcreteMachine:
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// MARK: - TimedMachine.
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void run_for(Cycles cycles) override {
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macro_counter_ += cycles.as<int>();
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while(macro_counter_ > 0) {
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macro_tick();
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}
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}
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void tick_cpu() {
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static uint32_t last_pc = 0;
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static bool log = false;
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auto instructions = cycles.as<int>();
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while(instructions) {
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auto run_length = std::min(timer_divider_, instructions);
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instructions -= run_length;
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timer_divider_ -= run_length;
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while(run_length--) {
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uint32_t instruction;
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pc_history[pc_history_ptr] = executor_.pc();
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pc_history_ptr = (pc_history_ptr + 1) % pc_history.size();
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@ -1132,20 +1290,6 @@ class ConcreteMachine:
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// }
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}
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if(log) {
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printf("");
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}
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if(!timer_divider_) {
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timer_divider_ = TimerTarget;
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if(executor_.bus.tick_timers()) {
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test_interrupts();
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}
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}
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}
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}
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void test_interrupts() {
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using Exception = InstructionSet::ARM::Registers::Exception;
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@ -1158,6 +1302,18 @@ class ConcreteMachine:
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}
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}
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void tick_timers() {
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if(executor_.bus.tick_timers()) {
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test_interrupts();
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}
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}
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void tick_audio() {
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if(executor_.bus.tick_audio()) {
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test_interrupts();
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}
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}
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// MARK: - MediaTarget
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bool insert_media(const Analyser::Static::Media &) override {
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// int c = 0;
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