mirror of
https://github.com/TomHarte/CLK.git
synced 2024-07-05 10:28:58 +00:00
Exposes non-BusOperation bus outputs.
This commit is contained in:
parent
334e0666b7
commit
096add7551
@ -25,6 +25,13 @@ using BusOperation = CPU::MOS6502Esque::BusOperation;
|
|||||||
using Register = CPU::MOS6502Esque::Register;
|
using Register = CPU::MOS6502Esque::Register;
|
||||||
using Flag = CPU::MOS6502Esque::Flag;
|
using Flag = CPU::MOS6502Esque::Flag;
|
||||||
|
|
||||||
|
enum ExtendedBusOutput {
|
||||||
|
Emulation = (1 << 0),
|
||||||
|
MemorySize = (1 << 1),
|
||||||
|
IndexSize = (1 << 2),
|
||||||
|
MemoryLock = (1 << 3),
|
||||||
|
};
|
||||||
|
|
||||||
#include "Implementation/65816Storage.hpp"
|
#include "Implementation/65816Storage.hpp"
|
||||||
|
|
||||||
class ProcessorBase: protected ProcessorStorage {
|
class ProcessorBase: protected ProcessorStorage {
|
||||||
@ -35,9 +42,18 @@ class ProcessorBase: protected ProcessorStorage {
|
|||||||
inline void set_reset_line(bool);
|
inline void set_reset_line(bool);
|
||||||
inline void set_abort_line(bool);
|
inline void set_abort_line(bool);
|
||||||
inline bool get_is_resetting() const;
|
inline bool get_is_resetting() const;
|
||||||
void set_value_of_register(Register r, uint16_t value);
|
|
||||||
|
|
||||||
|
/*!
|
||||||
|
Returns the current state of all lines not ordinarily pushed to the BusHandler.
|
||||||
|
*/
|
||||||
|
inline int get_extended_bus_output();
|
||||||
|
|
||||||
|
/*!
|
||||||
|
Provided for symmetry with the 6502; a 65816 is never jammed.
|
||||||
|
*/
|
||||||
inline bool is_jammed() const;
|
inline bool is_jammed() const;
|
||||||
|
|
||||||
|
void set_value_of_register(Register r, uint16_t value);
|
||||||
uint16_t get_value_of_register(Register r) const;
|
uint16_t get_value_of_register(Register r) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -55,6 +55,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
|
|||||||
instruction_buffer_.clear();
|
instruction_buffer_.clear();
|
||||||
data_buffer_.clear();
|
data_buffer_.clear();
|
||||||
last_operation_pc_ = registers_.pc;
|
last_operation_pc_ = registers_.pc;
|
||||||
|
memory_lock_ = false;
|
||||||
} continue;
|
} continue;
|
||||||
|
|
||||||
case OperationDecode: {
|
case OperationDecode: {
|
||||||
@ -176,6 +177,14 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
|
|||||||
|
|
||||||
#undef stack_access
|
#undef stack_access
|
||||||
|
|
||||||
|
//
|
||||||
|
// Memory lock control.
|
||||||
|
//
|
||||||
|
|
||||||
|
case OperationSetMemoryLock:
|
||||||
|
memory_lock_ = true;
|
||||||
|
continue;
|
||||||
|
|
||||||
//
|
//
|
||||||
// STP and WAI.
|
// STP and WAI.
|
||||||
//
|
//
|
||||||
@ -985,3 +994,11 @@ bool ProcessorBase::is_jammed() const { return false; }
|
|||||||
bool ProcessorBase::get_is_resetting() const {
|
bool ProcessorBase::get_is_resetting() const {
|
||||||
return pending_exceptions_ & (Reset | PowerOn);
|
return pending_exceptions_ & (Reset | PowerOn);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int ProcessorBase::get_extended_bus_output() {
|
||||||
|
return
|
||||||
|
(memory_lock_ ? ExtendedBusOutput::MemoryLock : 0) |
|
||||||
|
(registers_.mx_flags[0] ? ExtendedBusOutput::MemorySize : 0) |
|
||||||
|
(registers_.mx_flags[1] ? ExtendedBusOutput::IndexSize : 0) |
|
||||||
|
(registers_.emulation_flag ? ExtendedBusOutput::Emulation : 0);
|
||||||
|
}
|
||||||
|
@ -156,6 +156,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void read_modify_write(bool is8bit, const std::function<void(MicroOp)> &target) {
|
static void read_modify_write(bool is8bit, const std::function<void(MicroOp)> &target) {
|
||||||
|
target(OperationSetMemoryLock);
|
||||||
|
|
||||||
if(!is8bit) target(CycleFetchIncrementData); // Data low.
|
if(!is8bit) target(CycleFetchIncrementData); // Data low.
|
||||||
target(CycleFetchData); // Data [high].
|
target(CycleFetchData); // Data [high].
|
||||||
|
|
||||||
|
@ -149,6 +149,9 @@ enum MicroOp: uint8_t {
|
|||||||
/// address register.
|
/// address register.
|
||||||
OperationPrepareException,
|
OperationPrepareException,
|
||||||
|
|
||||||
|
/// Sets the memory lock output for the rest of this instruction.
|
||||||
|
OperationSetMemoryLock,
|
||||||
|
|
||||||
/// Complete this set of micr-ops.
|
/// Complete this set of micr-ops.
|
||||||
OperationMoveToNextProgram,
|
OperationMoveToNextProgram,
|
||||||
|
|
||||||
@ -289,6 +292,7 @@ struct ProcessorStorage {
|
|||||||
int selected_exceptions_ = 0;
|
int selected_exceptions_ = 0;
|
||||||
|
|
||||||
bool ready_line_ = false;
|
bool ready_line_ = false;
|
||||||
|
bool memory_lock_ = false;
|
||||||
|
|
||||||
// Just to be safe.
|
// Just to be safe.
|
||||||
static_assert(PowerOn != IRQ);
|
static_assert(PowerOn != IRQ);
|
||||||
|
Loading…
Reference in New Issue
Block a user