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Perform minor generalisation.

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This commit is contained in:
Thomas Harte 2023-08-17 14:50:43 -04:00
parent b9bd3f9b8c
commit 0a336baae2
1 changed files with 21 additions and 13 deletions
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34
OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm
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@ -14,16 +14,21 @@
#include <vector> #include <vector>
#include <unordered_map> #include <unordered_map>
#include "6502Selector.hpp"
namespace { namespace {
struct StopException {}; struct StopException {};
struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> { template <CPU::MOS6502Esque::Type type>
// Use a map to store RAM contents, in order to preserve initialised state. struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
std::unordered_map<uint32_t, uint8_t> ram; using AddressType = typename CPU::MOS6502Esque::BusHandlerT<type>::AddressType;
std::unordered_map<uint32_t, uint8_t> inventions;
Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, uint32_t address, uint8_t *value) { // Use a map to store RAM contents, in order to preserve initialised state.
std::unordered_map<AddressType, uint8_t> ram;
std::unordered_map<AddressType, uint8_t> inventions;
Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, AddressType address, uint8_t *value) {
// Record the basics of the operation. // Record the basics of the operation.
auto &cycle = cycles.emplace_back(); auto &cycle = cycles.emplace_back();
cycle.operation = operation; cycle.operation = operation;
@ -92,25 +97,27 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
allow_pc_repetition = opcode == 0x54 || opcode == 0x44; allow_pc_repetition = opcode == 0x54 || opcode == 0x44;
using Register = CPU::MOS6502Esque::Register; using Register = CPU::MOS6502Esque::Register;
const uint32_t pc = const auto pc =
processor.value_of(Register::ProgramCounter) | AddressT(
(processor.value_of(Register::ProgramBank) << 16); processor.value_of(Register::ProgramCounter) |
(processor.value_of(Register::ProgramBank) << 16)
);
inventions[pc] = ram[pc] = opcode; inventions[pc] = ram[pc] = opcode;
} }
int pc_overshoot = 0; int pc_overshoot = 0;
std::optional<uint32_t> initial_pc; std::optional<AddressType> initial_pc;
bool allow_pc_repetition = false; bool allow_pc_repetition = false;
struct Cycle { struct Cycle {
CPU::MOS6502Esque::BusOperation operation; CPU::MOS6502Esque::BusOperation operation;
std::optional<uint32_t> address; std::optional<AddressType> address;
std::optional<uint8_t> value; std::optional<uint8_t> value;
int extended_bus; int extended_bus;
}; };
std::vector<Cycle> cycles; std::vector<Cycle> cycles;
CPU::WDC65816::Processor<BusHandler, false> processor; CPU::MOS6502Esque::Processor<type, BusHandler<type>, false> processor;
BusHandler() : processor(*this) { BusHandler() : processor(*this) {
// Never run the official reset procedure. // Never run the official reset procedure.
@ -132,7 +139,8 @@ template <typename Processor> void print_registers(FILE *file, const Processor &
fprintf(file, "\"e\": %d, ", processor.value_of(Register::EmulationFlag)); fprintf(file, "\"e\": %d, ", processor.value_of(Register::EmulationFlag));
} }
void print_ram(FILE *file, const std::unordered_map<uint32_t, uint8_t> &data) { template <typename IntT>
void print_ram(FILE *file, const std::unordered_map<IntT, uint8_t> &data) {
fprintf(file, "\"ram\": ["); fprintf(file, "\"ram\": [");
bool is_first = true; bool is_first = true;
for(const auto &pair: data) { for(const auto &pair: data) {
@ -153,7 +161,7 @@ void print_ram(FILE *file, const std::unordered_map<uint32_t, uint8_t> &data) {
@implementation TestGenerator @implementation TestGenerator
- (void)generate { - (void)generate {
BusHandler handler; BusHandler<CPU::MOS6502Esque::Type::TWDC65816> handler;
NSString *const tempDir = NSTemporaryDirectory(); NSString *const tempDir = NSTemporaryDirectory();
NSLog(@"Outputting to %@", tempDir); NSLog(@"Outputting to %@", tempDir);