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Remove add_pc and decline_branch in favour of operation-specific signals.

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This commit is contained in:
Thomas Harte 2022-05-09 16:19:25 -04:00
parent 330ec1b848
commit 0af8660181
5 changed files with 42 additions and 45 deletions
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4
InstructionSets/M68k/Executor.hpp
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@ -49,12 +49,12 @@ template <Model model, typename BusHandler> class Executor {
// Flow control.
void consume_cycles(int) {}
void set_pc(uint32_t);
void add_pc(uint32_t);
void decline_branch() {}
void raise_exception(int, bool use_current_instruction_pc = true);
void did_update_status();
template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
void stop();
void bsr(uint32_t offset);
void jsr(uint32_t offset);

14
InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
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@ -330,7 +330,6 @@ void Executor<model, BusHandler>::set_state(const Registers &state) {
}
// MARK: - Flow Control.
// TODO: flow control, all below here.
template <Model model, typename BusHandler>
void Executor<model, BusHandler>::raise_exception(int index, bool use_current_instruction_pc) {
@ -367,8 +366,17 @@ void Executor<model, BusHandler>::set_pc(uint32_t address) {
}
template <Model model, typename BusHandler>
void Executor<model, BusHandler>::add_pc(uint32_t offset) {
program_counter_.l = instruction_address_ + offset;
template <typename IntT> void Executor<model, BusHandler>::complete_bcc(bool branch, IntT offset) {
if(branch) {
program_counter_.l = instruction_address_ + offset + 2;
}
}
template <Model model, typename BusHandler>
void Executor<model, BusHandler>::complete_dbcc(bool matched_condition, bool overflowed, int16_t offset) {
if(!matched_condition && !overflowed) {
program_counter_.l = instruction_address_ + offset + 2;
}
}
template <Model model, typename BusHandler>

63
InstructionSets/M68k/Implementation/PerformImplementation.hpp
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@ -254,27 +254,21 @@ template <
// Special case: the condition code is 1, which is ordinarily false. In that case this
// is the trailing step of a BSR.
case Operation::Bccb:
if(status.evaluate_condition(instruction.condition())) {
flow_controller.add_pc(int8_t(src.b) + 2);
} else {
flow_controller.decline_branch();
}
flow_controller.template complete_bcc<int8_t>(
status.evaluate_condition(instruction.condition()),
src.b);
break;
case Operation::Bccw:
if(status.evaluate_condition(instruction.condition())) {
flow_controller.add_pc(int16_t(src.w) + 2);
} else {
flow_controller.decline_branch();
}
flow_controller.template complete_bcc<int16_t>(
status.evaluate_condition(instruction.condition()),
src.w);
break;
case Operation::Bccl:
if(status.evaluate_condition(instruction.condition())) {
flow_controller.add_pc(src.l + 2);
} else {
flow_controller.decline_branch();
}
flow_controller.template complete_bcc<int32_t>(
status.evaluate_condition(instruction.condition()),
src.l);
break;
case Operation::BSRb:
@ -287,23 +281,22 @@ template <
flow_controller.bsr(src.l + 2);
break;
case Operation::DBcc:
// Decide what sort of DBcc this is.
if(!status.evaluate_condition(instruction.condition())) {
-- src.w;
case Operation::DBcc: {
const bool matched_condition = status.evaluate_condition(instruction.condition());
bool overflowed = false;
if(src.w == 0xffff) {
// This DBcc will be ignored as the counter has underflowed.
flow_controller.decline_branch();
} else {
// Take the branch.
flow_controller.add_pc(int16_t(dest.l) + 2);
}
} else {
// This DBcc will be ignored as the condition is true.
flow_controller.decline_branch();
// Classify the dbcc.
if(!matched_condition) {
-- src.w;
overflowed = src.w == 0xffff;
}
break;
// Take the branch.
flow_controller.complete_dbcc(
matched_condition,
overflowed,
int16_t(dest.w));
} break;
case Operation::Scc:
src.b = status.evaluate_condition(instruction.condition()) ? 0xff : 0x00;
@ -427,9 +420,9 @@ template <
dest.l = src.l;
break;
// case Operation::PEA:
// destination_bus_data_ = effective_address_[0];
// break;
case Operation::PEA:
flow_controller.pea(src.l);
break;
/*
Status word moves and manipulations.
@ -1205,10 +1198,6 @@ template <
flow_controller.template movem_toM<uint16_t>(instruction, src.l, dest.l);
break;
case Operation::PEA:
flow_controller.pea(src.l);
break;
/*
RTE and RTR share an implementation.
*/

2
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
View File

@ -30,7 +30,7 @@
- (void)setUp {
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
// _fileSet = [NSSet setWithArray:@[@"chk.json"]];
_fileSet = [NSSet setWithArray:@[@"dbcc.json"]];
// _testSet = [NSSet setWithArray:@[@"CHK 4190"]];
// _fileSet = [NSSet setWithArray:@[@"jmp_jsr.json"]];
// _testSet = [NSSet setWithArray:@[@"CHK 41a8"]];

4
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -1766,7 +1766,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
} break;
case Operation::ROLb: rol(destination()->halves.low.halves.low, 8); break;
case Operation::ROLw: rol(destination()->halves.low.full, 16); break;
case Operation::ROLl: rol(destination()->full, 32); break;
case Operation::ROLl: rol(destination()->full, 32); break;
#define ror(destination, size) { \
@ -1795,7 +1795,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
} break;
case Operation::RORb: ror(destination()->halves.low.halves.low, 8); break;
case Operation::RORw: ror(destination()->halves.low.full, 16); break;
case Operation::RORl: ror(destination()->full, 32); break;
case Operation::RORl: ror(destination()->full, 32); break;
#define roxl(destination, size) { \
decode_shift_count(); \