diff --git a/Components/9918/Implementation/PersonalityTraits.hpp b/Components/9918/Implementation/PersonalityTraits.hpp
index adc536192..6d035f7a4 100644
--- a/Components/9918/Implementation/PersonalityTraits.hpp
+++ b/Components/9918/Implementation/PersonalityTraits.hpp
@@ -38,6 +38,7 @@ constexpr size_t memory_size(Personality p) {
 		case TI::TMS::V9938:	return 128 * 1024;
 		case TI::TMS::V9958:	return 192 * 1024;
 	}
+	return 0;
 }
 
 constexpr size_t memory_mask(Personality p) {
diff --git a/InstructionSets/ARM/Executor.hpp b/InstructionSets/ARM/Executor.hpp
index 16c947d65..72c6770a3 100644
--- a/InstructionSets/ARM/Executor.hpp
+++ b/InstructionSets/ARM/Executor.hpp
@@ -337,9 +337,11 @@ struct Executor {
 			uint32_t value = 0;
 
 			if constexpr (flags.transfer_byte()) {
-				uint8_t target;
+				uint8_t target = 0;	// Value should never be used; this avoids a spurious GCC warning.
 				did_read = bus.template read<uint8_t>(address, target, registers_.mode(), trans);
-				value = target;
+				if(did_read) {
+					value = target;
+				}
 			} else {
 				did_read = bus.template read<uint32_t>(address, value, registers_.mode(), trans);
 
diff --git a/InstructionSets/ARM/Registers.hpp b/InstructionSets/ARM/Registers.hpp
index f1c690dd3..c3158b5d2 100644
--- a/InstructionSets/ARM/Registers.hpp
+++ b/InstructionSets/ARM/Registers.hpp
@@ -185,6 +185,7 @@ struct Registers {
 				// Unspecified; a guess.
 				case Exception::Reset:					return 0;
 			}
+			return 4;
 		}
 
 		/// Updates the program counter, interupt flags and link register if applicable to begin @c exception.
@@ -270,10 +271,11 @@ struct Registers {
 				case Condition::GT:	return !le();
 				case Condition::LE:	return le();
 
-				default:
 				case Condition::AL:	return true;
 				case Condition::NV:	return false;
 			}
+
+			return false;
 		}
 
 		/// Sets current execution mode.
@@ -345,23 +347,19 @@ struct Registers {
 		/// this will the the user-mode register. Otherwise it'll be that for the current mode. These references
 		/// are guaranteed to remain valid only until the next mode change.
 		uint32_t &reg(bool force_user_mode, uint32_t offset) {
-			if(!force_user_mode) {
-				return active_[offset];
-			}
-
 			switch(mode_) {
 				default:
 				case Mode::User: return active_[offset];
 
 				case Mode::Supervisor:
 				case Mode::IRQ:
-					if(offset == 13 || offset == 14) {
+					if(force_user_mode && (offset == 13 || offset == 14)) {
 						return user_registers_[offset - 8];
 					}
 					return active_[offset];
 
 				case Mode::FIQ:
-					if(offset >= 8 && offset < 15) {
+					if(force_user_mode && (offset >= 8 && offset < 15)) {
 						return user_registers_[offset - 8];
 					}
 					return active_[offset];
diff --git a/Machines/Acorn/Archimedes/Archimedes.cpp b/Machines/Acorn/Archimedes/Archimedes.cpp
index f9fe9b5bf..b44dfecdc 100644
--- a/Machines/Acorn/Archimedes/Archimedes.cpp
+++ b/Machines/Acorn/Archimedes/Archimedes.cpp
@@ -548,10 +548,10 @@ class ConcreteMachine:
 		}
 
 		uint32_t advance_pipeline(uint32_t pc) {
-			uint32_t instruction;
+			uint32_t instruction = 0;	// Value should never be used; this avoids a spurious GCC warning.
 			const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
 			return pipeline_.exchange(
-				instruction,
+				did_read ? instruction : Pipeline::SWI,
 				did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
 		}
 
@@ -563,6 +563,8 @@ class ConcreteMachine:
 				FIQ,
 			};
 
+			static constexpr uint32_t SWI = 0xef'000000;
+
 			uint32_t exchange(uint32_t next, SWISubversion subversion) {
 				const uint32_t result = upcoming_[active_].opcode;
 				latched_subversion_ = upcoming_[active_].subversion;
@@ -586,7 +588,7 @@ class ConcreteMachine:
 			// In practice I got into a bit of a race condition between interrupt scheduling and
 			// flags changes, so have backed off for now.
 			void reschedule(SWISubversion subversion) {
-				upcoming_[active_].opcode = 0xef'000000;
+				upcoming_[active_].opcode = SWI;
 				upcoming_[active_].subversion = subversion;
 			}
 
diff --git a/Machines/Apple/AppleIIgs/MemoryMap.hpp b/Machines/Apple/AppleIIgs/MemoryMap.hpp
index ab5b01b0a..363758475 100644
--- a/Machines/Apple/AppleIIgs/MemoryMap.hpp
+++ b/Machines/Apple/AppleIIgs/MemoryMap.hpp
@@ -77,8 +77,8 @@ class MemoryMap {
 			}
 
 			const auto physical = physical_address(region, address);
-			assert(physical >= 0 && physical <= 0xff'ffff);
-			return shadow_pages_[(physical >> 10) & 127] & shadow_banks_[physical >> 17];
+			assert(physical <= 0xff'ffff);
+			return shadow_pages_[(physical >> 10) & 127] && shadow_banks_[physical >> 17];
 		}
 		void write(const Region &region, uint32_t address, uint8_t value) {
 			if(!region.write) {
diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index 977f0cc11..18db92beb 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -1869,6 +1869,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 					SetupDataAccess(0, Operation::SelectWord);
 				MoveToStateSpecific(StoreOperand_l);
 
+				default:	// Convince GCC that nothing here is amiss.
 				case InstructionSet::M68k::DataSize::Word:
 					SetupDataAccess(0, Operation::SelectWord);
 				MoveToStateSpecific(StoreOperand_bw);