From 8e64a854fc410983e9f6038122a9eae7512ef1f1 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 21:56:53 -0400 Subject: [PATCH 1/8] Ensure all routes return; mildly decrease conditionals. --- InstructionSets/ARM/Registers.hpp | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/InstructionSets/ARM/Registers.hpp b/InstructionSets/ARM/Registers.hpp index f1c690dd3..c3158b5d2 100644 --- a/InstructionSets/ARM/Registers.hpp +++ b/InstructionSets/ARM/Registers.hpp @@ -185,6 +185,7 @@ struct Registers { // Unspecified; a guess. case Exception::Reset: return 0; } + return 4; } /// Updates the program counter, interupt flags and link register if applicable to begin @c exception. @@ -270,10 +271,11 @@ struct Registers { case Condition::GT: return !le(); case Condition::LE: return le(); - default: case Condition::AL: return true; case Condition::NV: return false; } + + return false; } /// Sets current execution mode. @@ -345,23 +347,19 @@ struct Registers { /// this will the the user-mode register. Otherwise it'll be that for the current mode. These references /// are guaranteed to remain valid only until the next mode change. uint32_t ®(bool force_user_mode, uint32_t offset) { - if(!force_user_mode) { - return active_[offset]; - } - switch(mode_) { default: case Mode::User: return active_[offset]; case Mode::Supervisor: case Mode::IRQ: - if(offset == 13 || offset == 14) { + if(force_user_mode && (offset == 13 || offset == 14)) { return user_registers_[offset - 8]; } return active_[offset]; case Mode::FIQ: - if(offset >= 8 && offset < 15) { + if(force_user_mode && (offset >= 8 && offset < 15)) { return user_registers_[offset - 8]; } return active_[offset]; From c91ce4cfeafd8eb9e33c7da8ad5314e9b3422987 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 21:57:20 -0400 Subject: [PATCH 2/8] Ensure all routes return. --- Components/9918/Implementation/PersonalityTraits.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Components/9918/Implementation/PersonalityTraits.hpp b/Components/9918/Implementation/PersonalityTraits.hpp index adc536192..6d035f7a4 100644 --- a/Components/9918/Implementation/PersonalityTraits.hpp +++ b/Components/9918/Implementation/PersonalityTraits.hpp @@ -38,6 +38,7 @@ constexpr size_t memory_size(Personality p) { case TI::TMS::V9938: return 128 * 1024; case TI::TMS::V9958: return 192 * 1024; } + return 0; } constexpr size_t memory_mask(Personality p) { From f86e9fe086e9b4cec8472af26dbbf858cdf8e348 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 21:58:49 -0400 Subject: [PATCH 3/8] Eliminate impossible conditional. --- Machines/Apple/AppleIIgs/MemoryMap.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Machines/Apple/AppleIIgs/MemoryMap.hpp b/Machines/Apple/AppleIIgs/MemoryMap.hpp index ab5b01b0a..d5676ad20 100644 --- a/Machines/Apple/AppleIIgs/MemoryMap.hpp +++ b/Machines/Apple/AppleIIgs/MemoryMap.hpp @@ -77,7 +77,7 @@ class MemoryMap { } const auto physical = physical_address(region, address); - assert(physical >= 0 && physical <= 0xff'ffff); + assert(physical <= 0xff'ffff); return shadow_pages_[(physical >> 10) & 127] & shadow_banks_[physical >> 17]; } void write(const Region ®ion, uint32_t address, uint8_t value) { From c485097eed68c9ecf5841a356dedc842adf10a5a Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 22:06:09 -0400 Subject: [PATCH 4/8] Fix bool combination. --- Machines/Apple/AppleIIgs/MemoryMap.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Machines/Apple/AppleIIgs/MemoryMap.hpp b/Machines/Apple/AppleIIgs/MemoryMap.hpp index d5676ad20..363758475 100644 --- a/Machines/Apple/AppleIIgs/MemoryMap.hpp +++ b/Machines/Apple/AppleIIgs/MemoryMap.hpp @@ -78,7 +78,7 @@ class MemoryMap { const auto physical = physical_address(region, address); assert(physical <= 0xff'ffff); - return shadow_pages_[(physical >> 10) & 127] & shadow_banks_[physical >> 17]; + return shadow_pages_[(physical >> 10) & 127] && shadow_banks_[physical >> 17]; } void write(const Region ®ion, uint32_t address, uint8_t value) { if(!region.write) { From 265d1518799361723ce72d0baba01a61d09824db Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 22:08:09 -0400 Subject: [PATCH 5/8] Fix data aborts. --- Machines/Acorn/Archimedes/Archimedes.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Machines/Acorn/Archimedes/Archimedes.cpp b/Machines/Acorn/Archimedes/Archimedes.cpp index f9fe9b5bf..85dd4ddc4 100644 --- a/Machines/Acorn/Archimedes/Archimedes.cpp +++ b/Machines/Acorn/Archimedes/Archimedes.cpp @@ -551,7 +551,7 @@ class ConcreteMachine: uint32_t instruction; const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false); return pipeline_.exchange( - instruction, + did_read ? instruction : Pipeline::SWI, did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort); } @@ -563,6 +563,8 @@ class ConcreteMachine: FIQ, }; + static constexpr uint32_t SWI = 0xef'000000; + uint32_t exchange(uint32_t next, SWISubversion subversion) { const uint32_t result = upcoming_[active_].opcode; latched_subversion_ = upcoming_[active_].subversion; @@ -586,7 +588,7 @@ class ConcreteMachine: // In practice I got into a bit of a race condition between interrupt scheduling and // flags changes, so have backed off for now. void reschedule(SWISubversion subversion) { - upcoming_[active_].opcode = 0xef'000000; + upcoming_[active_].opcode = SWI; upcoming_[active_].subversion = subversion; } From 56b65780d2c795813dfe33ff33b23bc5615e251e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 22 Apr 2024 22:09:57 -0400 Subject: [PATCH 6/8] Avoid loading nonsense value upon data abort. --- InstructionSets/ARM/Executor.hpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/InstructionSets/ARM/Executor.hpp b/InstructionSets/ARM/Executor.hpp index 16c947d65..af997a4d5 100644 --- a/InstructionSets/ARM/Executor.hpp +++ b/InstructionSets/ARM/Executor.hpp @@ -339,7 +339,9 @@ struct Executor { if constexpr (flags.transfer_byte()) { uint8_t target; did_read = bus.template read(address, target, registers_.mode(), trans); - value = target; + if(did_read) { + value = target; + } } else { did_read = bus.template read(address, value, registers_.mode(), trans); From becb6ce2e027e9f02c46b22443c06df1c445b60d Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 23 Apr 2024 22:20:13 -0400 Subject: [PATCH 7/8] Fix two more not-really-an-issue warnings. --- InstructionSets/ARM/Executor.hpp | 2 +- Machines/Acorn/Archimedes/Archimedes.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/InstructionSets/ARM/Executor.hpp b/InstructionSets/ARM/Executor.hpp index af997a4d5..72c6770a3 100644 --- a/InstructionSets/ARM/Executor.hpp +++ b/InstructionSets/ARM/Executor.hpp @@ -337,7 +337,7 @@ struct Executor { uint32_t value = 0; if constexpr (flags.transfer_byte()) { - uint8_t target; + uint8_t target = 0; // Value should never be used; this avoids a spurious GCC warning. did_read = bus.template read(address, target, registers_.mode(), trans); if(did_read) { value = target; diff --git a/Machines/Acorn/Archimedes/Archimedes.cpp b/Machines/Acorn/Archimedes/Archimedes.cpp index 85dd4ddc4..b44dfecdc 100644 --- a/Machines/Acorn/Archimedes/Archimedes.cpp +++ b/Machines/Acorn/Archimedes/Archimedes.cpp @@ -548,7 +548,7 @@ class ConcreteMachine: } uint32_t advance_pipeline(uint32_t pc) { - uint32_t instruction; + uint32_t instruction = 0; // Value should never be used; this avoids a spurious GCC warning. const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false); return pipeline_.exchange( did_read ? instruction : Pipeline::SWI, From 36d9c40d7b369a118024c21a89e0b759d6151546 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 23 Apr 2024 22:23:56 -0400 Subject: [PATCH 8/8] Yuckily avoid warning. --- Processors/68000/Implementation/68000Implementation.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp index 977f0cc11..18db92beb 100644 --- a/Processors/68000/Implementation/68000Implementation.hpp +++ b/Processors/68000/Implementation/68000Implementation.hpp @@ -1869,6 +1869,7 @@ void Processor