mirror of https://github.com/TomHarte/CLK.git
Merge pull request #1364 from TomHarte/SomeWarnings
Resolve various warnings.
This commit is contained in:
commit
0bff2089c4
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@ -38,6 +38,7 @@ constexpr size_t memory_size(Personality p) {
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case TI::TMS::V9938: return 128 * 1024;
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case TI::TMS::V9938: return 128 * 1024;
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case TI::TMS::V9958: return 192 * 1024;
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case TI::TMS::V9958: return 192 * 1024;
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}
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}
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return 0;
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}
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}
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constexpr size_t memory_mask(Personality p) {
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constexpr size_t memory_mask(Personality p) {
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@ -337,9 +337,11 @@ struct Executor {
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uint32_t value = 0;
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uint32_t value = 0;
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if constexpr (flags.transfer_byte()) {
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if constexpr (flags.transfer_byte()) {
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uint8_t target;
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uint8_t target = 0; // Value should never be used; this avoids a spurious GCC warning.
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did_read = bus.template read<uint8_t>(address, target, registers_.mode(), trans);
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did_read = bus.template read<uint8_t>(address, target, registers_.mode(), trans);
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value = target;
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if(did_read) {
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value = target;
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}
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} else {
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} else {
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did_read = bus.template read<uint32_t>(address, value, registers_.mode(), trans);
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did_read = bus.template read<uint32_t>(address, value, registers_.mode(), trans);
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@ -185,6 +185,7 @@ struct Registers {
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// Unspecified; a guess.
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// Unspecified; a guess.
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case Exception::Reset: return 0;
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case Exception::Reset: return 0;
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}
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}
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return 4;
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}
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}
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/// Updates the program counter, interupt flags and link register if applicable to begin @c exception.
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/// Updates the program counter, interupt flags and link register if applicable to begin @c exception.
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@ -270,10 +271,11 @@ struct Registers {
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case Condition::GT: return !le();
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case Condition::GT: return !le();
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case Condition::LE: return le();
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case Condition::LE: return le();
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default:
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case Condition::AL: return true;
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case Condition::AL: return true;
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case Condition::NV: return false;
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case Condition::NV: return false;
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}
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}
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return false;
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}
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}
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/// Sets current execution mode.
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/// Sets current execution mode.
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@ -345,23 +347,19 @@ struct Registers {
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/// this will the the user-mode register. Otherwise it'll be that for the current mode. These references
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/// this will the the user-mode register. Otherwise it'll be that for the current mode. These references
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/// are guaranteed to remain valid only until the next mode change.
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/// are guaranteed to remain valid only until the next mode change.
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uint32_t ®(bool force_user_mode, uint32_t offset) {
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uint32_t ®(bool force_user_mode, uint32_t offset) {
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if(!force_user_mode) {
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return active_[offset];
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}
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switch(mode_) {
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switch(mode_) {
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default:
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default:
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case Mode::User: return active_[offset];
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case Mode::User: return active_[offset];
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case Mode::Supervisor:
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case Mode::Supervisor:
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case Mode::IRQ:
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case Mode::IRQ:
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if(offset == 13 || offset == 14) {
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if(force_user_mode && (offset == 13 || offset == 14)) {
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return user_registers_[offset - 8];
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return user_registers_[offset - 8];
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}
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}
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return active_[offset];
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return active_[offset];
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case Mode::FIQ:
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case Mode::FIQ:
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if(offset >= 8 && offset < 15) {
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if(force_user_mode && (offset >= 8 && offset < 15)) {
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return user_registers_[offset - 8];
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return user_registers_[offset - 8];
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}
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}
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return active_[offset];
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return active_[offset];
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@ -548,10 +548,10 @@ class ConcreteMachine:
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}
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}
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uint32_t advance_pipeline(uint32_t pc) {
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uint32_t advance_pipeline(uint32_t pc) {
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uint32_t instruction;
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uint32_t instruction = 0; // Value should never be used; this avoids a spurious GCC warning.
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
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return pipeline_.exchange(
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return pipeline_.exchange(
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instruction,
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did_read ? instruction : Pipeline::SWI,
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did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
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did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
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}
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}
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@ -563,6 +563,8 @@ class ConcreteMachine:
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FIQ,
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FIQ,
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};
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};
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static constexpr uint32_t SWI = 0xef'000000;
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uint32_t exchange(uint32_t next, SWISubversion subversion) {
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uint32_t exchange(uint32_t next, SWISubversion subversion) {
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const uint32_t result = upcoming_[active_].opcode;
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const uint32_t result = upcoming_[active_].opcode;
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latched_subversion_ = upcoming_[active_].subversion;
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latched_subversion_ = upcoming_[active_].subversion;
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@ -586,7 +588,7 @@ class ConcreteMachine:
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// In practice I got into a bit of a race condition between interrupt scheduling and
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// In practice I got into a bit of a race condition between interrupt scheduling and
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// flags changes, so have backed off for now.
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// flags changes, so have backed off for now.
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void reschedule(SWISubversion subversion) {
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void reschedule(SWISubversion subversion) {
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upcoming_[active_].opcode = 0xef'000000;
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upcoming_[active_].opcode = SWI;
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upcoming_[active_].subversion = subversion;
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upcoming_[active_].subversion = subversion;
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}
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}
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@ -77,8 +77,8 @@ class MemoryMap {
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}
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}
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const auto physical = physical_address(region, address);
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const auto physical = physical_address(region, address);
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assert(physical >= 0 && physical <= 0xff'ffff);
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assert(physical <= 0xff'ffff);
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return shadow_pages_[(physical >> 10) & 127] & shadow_banks_[physical >> 17];
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return shadow_pages_[(physical >> 10) & 127] && shadow_banks_[physical >> 17];
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}
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}
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void write(const Region ®ion, uint32_t address, uint8_t value) {
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void write(const Region ®ion, uint32_t address, uint8_t value) {
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if(!region.write) {
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if(!region.write) {
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@ -1869,6 +1869,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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SetupDataAccess(0, Operation::SelectWord);
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SetupDataAccess(0, Operation::SelectWord);
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MoveToStateSpecific(StoreOperand_l);
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MoveToStateSpecific(StoreOperand_l);
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default: // Convince GCC that nothing here is amiss.
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case InstructionSet::M68k::DataSize::Word:
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case InstructionSet::M68k::DataSize::Word:
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SetupDataAccess(0, Operation::SelectWord);
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SetupDataAccess(0, Operation::SelectWord);
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MoveToStateSpecific(StoreOperand_bw);
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MoveToStateSpecific(StoreOperand_bw);
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