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Shortens impact of MULU on the instruction stream to correct parsing.

I need to look into this.
This commit is contained in:
Thomas Harte 2019-04-17 15:15:48 -04:00
parent 0bd653708c
commit 0c05983617
2 changed files with 3 additions and 5 deletions

View File

@ -52,7 +52,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// no instruction was ongoing. Either way, do a standard instruction operation. // no instruction was ongoing. Either way, do a standard instruction operation.
// TODO: unless an interrupt is pending, or the trap flag is set. // TODO: unless an interrupt is pending, or the trap flag is set.
// if(program_counter_.full >= 0x25c && program_counter_.full < 0x286) { // if(program_counter_.full >= 0x250 && program_counter_.full <= 0x25e) {
// std::cout << std::setfill('0'); // std::cout << std::setfill('0');
// std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z'); // std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
// std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t'; // std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
@ -73,9 +73,6 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
active_program_ = &instructions[decoded_instruction_]; active_program_ = &instructions[decoded_instruction_];
active_micro_op_ = active_program_->micro_operations; active_micro_op_ = active_program_->micro_operations;
if(decoded_instruction_ == 0xd1ae) {
printf("");
}
} }
auto bus_program = active_micro_op_->bus_program; auto bus_program = active_micro_op_->bus_program;

View File

@ -639,7 +639,8 @@ struct ProcessorStorageConstructor {
break; break;
case Imm: case Imm:
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np np")); // DEVIATION FROM YACHT.TXT. It has an additional np, which I need to figure out.
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op(Action::PerformOperation, seq("r")); op(Action::PerformOperation, seq("r"));
break; break;
} }