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Resolve type mismatches.

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This commit is contained in:
Thomas Harte 2024-03-04 13:53:46 -05:00
parent 61d4c69e45
commit 0cdca12e06
2 changed files with 12 additions and 12 deletions
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10
InstructionSets/ARM/OperationMapper.hpp
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@ -81,7 +81,7 @@ struct Branch {
constexpr Branch(uint32_t opcode) noexcept : opcode_(opcode) {}
/// The 26-bit offset to add to the PC.
int offset() const { return (opcode_ & 0xff'ffff) << 2; }
uint32_t offset() const { return (opcode_ & 0xff'ffff) << 2; }
private:
uint32_t opcode_;
@ -170,7 +170,7 @@ struct DataProcessing: public WithShiftControlBits {
//
/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
int immediate() const { return opcode_ & 0xff; }
uint32_t immediate() const { return opcode_ & 0xff; }
/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
int rotate() const { return (opcode_ >> 7) & 0x1e; }
};
@ -255,7 +255,7 @@ struct SingleDataTransfer: public WithShiftControlBits {
int base() const { return (opcode_ >> 16) & 0xf; }
/// The immediate offset, if @c offset_is_register() was @c false; meaningless otherwise.
int immediate() const { return opcode_ & 0xfff; }
uint32_t immediate() const { return opcode_ & 0xfff; }
};
//
@ -286,10 +286,10 @@ struct BlockDataTransfer: public WithShiftControlBits {
using WithShiftControlBits::WithShiftControlBits;
/// The base register index. i.e. 'Rn'.
int base() const { return (opcode_ >> 16) & 0xf; }
int base() const { return (opcode_ >> 16) & 0xf; }
/// A bitfield indicating which registers to load or store.
int register_list() const { return opcode_ & 0xffff; }
uint16_t register_list() const { return static_cast<uint16_t>(opcode_); }
};
//

14
InstructionSets/ARM/Registers.hpp
View File

@ -17,13 +17,13 @@ namespace InstructionSet::ARM {
namespace ConditionCode {
static constexpr uint32_t Negative = 1 << 31;
static constexpr uint32_t Zero = 1 << 30;
static constexpr uint32_t Carry = 1 << 29;
static constexpr uint32_t Overflow = 1 << 28;
static constexpr uint32_t IRQDisable = 1 << 27;
static constexpr uint32_t FIQDisable = 1 << 26;
static constexpr uint32_t Mode = (1 << 1) | (1 << 0);
static constexpr uint32_t Negative = 1u << 31;
static constexpr uint32_t Zero = 1u << 30;
static constexpr uint32_t Carry = 1u << 29;
static constexpr uint32_t Overflow = 1u << 28;
static constexpr uint32_t IRQDisable = 1u << 27;
static constexpr uint32_t FIQDisable = 1u << 26;
static constexpr uint32_t Mode = (1u << 1) | (1u << 0);
static constexpr uint32_t Address = FIQDisable - Mode - 1;