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Corrects delay for SN access.

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This commit is contained in:
Thomas Harte 2019-02-27 22:58:43 -05:00
parent 56e691f256
commit 0dbd8a667d
1 changed files with 6 additions and 5 deletions
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11
Machines/ColecoVision/ColecoVision.cpp
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@ -191,12 +191,13 @@ class ConcreteMachine:
// MARK: Z80::BusHandler // MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) { forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// The SN76489 will use its ready line to trigger the Z80's wait for three // The SN76489 will use its ready line to trigger the Z80's wait, which will add
// cycles when accessed. M1 cycles are extended by a single cycle. Short-circuit // thirty-one (!) cycles when accessed. M1 cycles are extended by a single cycle.
// that whole piece of communications by just accruing the time here if applicable. // This code works out the delay up front in order to simplify execution flow, though
// technically this is a little duplicative.
HalfCycles penalty(0); HalfCycles penalty(0);
if(cycle.operation == CPU::Z80::PartialMachineCycle::Output && ((*cycle.address >> 5) & 7) == 7) { if((cycle.operation == CPU::Z80::PartialMachineCycle::Output || cycle.operation == CPU::Z80::PartialMachineCycle::Input) && ((*cycle.address >> 5) & 7) == 7) {
penalty = HalfCycles(6); penalty = HalfCycles(62);
} else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) { } else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) {
penalty = HalfCycles(2); penalty = HalfCycles(2);
} }